Datasheet

AD1937

Rev. B | Page 28 of 36

Table 23. PLL and Clock Control 1 Register (Address 1, 0x01)

Bit Value Function Description

0 0 PLL clock DAC clock source select

1 MCLK

1 0 PLL clock ADC clock source select

1 MCLK

2 0 Enabled On-chip voltage reference

1 Disabled

3 0 Not locked PLL lock indicator (read-only)

1 Locked

7:4 0000 Reserved

DAC CONTROL REGISTERS

Table 24. DAC Control 0 Register (Address 2, 0x02)

Bit Value Function Description

0 0 Normal Power-down

1 Power-down

2:1 00 32 kHz/44.1 kHz/48 kHz Sample rate

01 64 kHz/88.2 kHz/96 kHz

10 128 kHz/176.4 kHz/192 kHz

11 Reserved

5:3 000 1 cycle (I

S mode) DSDATA delay (BCLK periods)

001 0 (left-justified mode)

010 8 cycles (right-justified 24-bit mode)

011 12 cycles (right-justified 20-bit mode)

100 16 cycles (right-justified 16-bit mode)

101 Reserved

110 Reserved

111 Reserved

7:6 00 Stereo (normal) Serial format

01 TDM single-line, standalone, and daisy-chain modes

10 TDM/AUX mode (ADC-, DAC-, TDM-coupled)

11 TDM dual-line daisy-chain mode