Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD1937WBSTZ

Four ADCs/Eight DACs with PLL,

192 kHz, 24-Bit Codec

AD1937

Rev. B

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FEATURES

PLL-generated clock or direct master clock

Low EMI design

112 dB DAC/107 dB ADC dynamic range and SNR

−96 dB THD + N

Single 3.3 V supply

Tolerance for 5 V logic inputs

Supports 24-bits and 8 kHz to 192 kHz sample rates

Differential ADC input

Differential DAC output

Log volume control with autoramp function

C-controllable for flexibility

Software-controllable clickless mute

Software power-down

Right-justified, left-justified, I

S, and TDM modes

Master and slave modes up to 16-channel input/output

Available in a 64-lead LQFP

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Home theater systems

Set-top boxes

Digital audio effects processors

GENERAL DESCRIPTION

The AD1937 is a high performance, single-chip codec that provides

four analog-to-digital converters (ADCs) with differential input

and eight digital-to-analog converters (DACs) with differential

output, using the Analog Devices, Inc., patented multibit sigma-

delta (Σ-Δ) architecture. An I

C® port is included, allowing a

microcontroller to adjust volume and many other parameters.

The AD1937 operates from 3.3 V digital and analog supplies.

The AD1937 is available in a 64-lead (differential output) LQFP.

The AD1937 is designed for low EMI. This consideration is

apparent in both the system and circuit design architectures.

By using the on-board PLL to derive the master clock from the

LR (frame) clock or from an external crystal, the AD1937 elimi-

nates the need for a separate high frequency master clock and

can also be used with a suppressed bit clock. The DACs and

ADCs are designed using the latest Analog Devices continuous

time architecture to further minimize EMI. By using 3.3 V

supplies, power consumption is minimized and further

reduces emissions.

FUNCTIONAL BLOCK DIAGRAM

SERIAL DATA PORT

DIGITAL AUDIO

INPUT/OUTPUT

DIGITAL

FILTER

PRECISION

VOLTAGE

REFERENCE

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL)

CONTROL PORT

AD1937

DAC

CONTROL DATA

INPUT/OUTPUT

ADC

NALOG

AUDIO

INPUTS

ANALOG

AUDIO

OUTPUTS

DAC

SDATA

OUT

SDATA

CLOCKS

DIGITAL

FILTER

AND

VOLUME

CONTROL

07414-001

Figure 1.

Summary of content (36 pages)

PAGE 1
Four ADCs/Eight DACs with PLL, 192 kHz, 24-Bit Codec AD1937 FEATURES GENERAL DESCRIPTION PLL-generated clock or direct master clock Low EMI design 112 dB DAC/107 dB ADC dynamic range and SNR −96 dB THD + N Single 3.
PAGE 2
AD1937 TABLE OF CONTENTS Features .............................................................................................. 1 Analog-to-Digital Converters (ADCs) .................................... 15 Applications ....................................................................................... 1 Digital-to-Analog Converters (DACs) .................................... 15 General Description ......................................................................... 1 Clock Signals ...........
PAGE 3
AD1937 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Table 1. Parameter Supply Voltages (AVDD, DVDD) Temperature Master Clock Input Sample Rate Measurement Bandwidth Word Width Load Capacitance (Digital Output) Load Current (Digital Output) Input Voltage High Input Voltage Low Value 3.3 V As specified in Table 2 and Table 3 12.
PAGE 4
AD1937 Parameter Total Harmonic Distortion + Noise Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset Error Gain Drift Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output REGULATOR Input Supply Voltage Regulated Output Voltage Conditions/Comments 0 dBFS Two channels running Eight channels running Min
PAGE 5
AD1937 Parameter Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset Error Gain Drift Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output REGULATOR Input Supply Voltage Regulated Output Voltage −40°C < TC < +125°C, AVDD = 3.3 V ± 10% Min Max 1.6 1.9 −10 +10 −0.2 +0.
PAGE 6
AD1937 DIGITAL SPECIFICATIONS −40°C < TC < +125°C, DVDD = 3.3 V ± 10%. Table 5. Parameter INPUT High Level Input Voltage (VIH) Low Level Input Voltage (VIL) Input Leakage Input Capacitance OUTPUT High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Conditions/Comments Min MCLKI/MCLKXI pin 2.0 2.2 Typ IIH @ VIH = 2.4 V IIL @ VIL = 0.8 V Max Unit 0.8 10 10 5 V V V μA μA pF 0.4 V V IOH = 1 mA IOL = 1 mA DVDD − 0.
PAGE 7
AD1937 DIGITAL FILTERS Table 7. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode All modes, typical @ 48 kHz Factor Min 0.4375 × fS Typ Max 21 ±0.015 24 27 0.5 × fS 0.5625 × fS kHz dB kHz kHz dB μs 79 22.
PAGE 8
AD1937 TIMING SPECIFICATIONS −40°C < TC < +125°C, DVDD = 3.3 V ± 10%. Table 8. Parameter INPUT MASTER CLOCK (MCLK) AND RESET tMH Condition Comments Min Max Unit MCLK duty cycle DAC/ADC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, and 768 fS DAC/ADC clock source = direct MCLK @ 512 fS (bypass on-chip PLL) PLL mode, 256 fS reference Direct 512 fS mode 40 60 % 40 60 % 6.9 13.8 27.6 MHz MHz ns tMCLK 10 60 ms % 400 1.
PAGE 9
AD1937 TIMING DIAGRAMS tDBH DBCLK tDBL tDLH tDLS DLRCLK tDDS DSDATAx LEFT-JUSTIFIED MODE MSB – 1 MSB tDDH tDDS DSDATAx I2S-JUSTIFIED MODE MSB tDDH tDDS MSB LSB tDDH tDDH 07414-025 tDDS DSDATAx RIGHT-JUSTIFIED MODE Figure 2. DAC Serial Timing tABH ABCLK tABL tALH tALS ALRCLK tABDD ASDATAx LEFT-JUSTIFIED MODE MSB MSB – 1 tABDD ASDATAx I2S-JUSTIFIED MODE MSB ASDATAx RIGHT-JUSTIFIED MODE MSB Figure 3. ADC Serial Timing Rev.
PAGE 10
AD1937 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 9. Parameter Analog (AVDD) Digital (DVDD) VSUPPLY Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +6.0 V ±20 mA –0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.
PAGE 11
AD1937 NC NC AVDD LF ADC2RN ADC2RP ADC2LN ADC2LP ADC1RN ADC1RP ADC1LN ADC1LP CM AVDD NC NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 AGND 2 47 FILTR MCLKO/MCLKXO 3 46 AGND AGND 4 45 AVDD AVDD 5 44 AGND DAC3LP 6 43 DAC2RN DAC3LN 7 42 DAC2RP DAC3RP 8 41 DAC2LN DAC3RN 9 40 DAC2LP DAC4LP 10 39 DAC1RN DAC4LN 11 38 DAC1RP DAC4RP 12 37 DAC1LN DAC4RN 13 36 DAC1LP PD/RST 14 35 ADDR1
PAGE 12
AD1937 Pin No. 23 24 25 26 Type 1 I I O I/O Mnemonic VSUPPLY VSENSE VDRIVE ASDATA2 27 28 29 30 31 34 35 36 37 38 39 40 41 42 43 47 49, 50, 63, 64 52 53 54 55 56 57 58 59 60 61 O I/O I/O I I/O I I O O O O O O O O O ASDATA1 ABCLK ALRCLK ADDR0 SDA SCL ADDR1 DAC1LP DAC1LN DAC1RP DAC1RN DAC2LP DAC2LN DAC2RP DAC2RN FILTR NC CM ADC1LP ADC1LN ADC1RP ADC1RN ADC2LP ADC2LN ADC2RP ADC2RN LF 1 O I I I I I I I I O Description 5 V Input to Regulator, Emitter of Pass Transistor. Connect 3.
PAGE 13
AD1937 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0 0.08 0.06 MAGNITUDE (dB) MAGNITUDE (dB) 0.04 0.02 0 –0.02 –0.04 –50 –100 –0.06 –150 0 2 4 6 8 10 12 14 16 07414-003 –0.10 18 FREQUENCY (kHz) 0 12 24 36 48 FREQUENCY (kHz) Figure 5. ADC Pass-Band Filter Response, 48 kHz 07414-006 –0.08 Figure 8. DAC Stop-Band Filter Response, 48 kHz 0.10 0 –10 –20 0.05 MAGNITUDE (dB) MAGNITUDE (dB) –30 –40 –50 –60 –70 0 –0.05 –80 0 5 10 15 20 25 30 35 –0.
PAGE 14
AD1937 0.5 0 0.4 0.3 –2 MAGNITUDE (dB) 0.1 0 –0.1 –4 –6 –0.2 –8 –0.3 –0.5 0 8 16 32 64 FREQUENCY (kHz) –10 48 64 80 FREQUENCY (kHz) Figure 12. DAC Stop-Band Filter Response, 192 kHz Figure 11. DAC Pass-Band Filter Response, 192 kHz Rev. B | Page 14 of 36 96 07414-010 –0.4 07414-009 MAGNITUDE (dB) 0.
PAGE 15
AD1937 THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCs) There are four ADC channels in the AD1937 configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs include on-board digital antialiasing filters with 79 dB stopband attenuation and linear phase response, operating at an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes).
PAGE 16
AD1937 To maintain the highest performance possible, limit the clock jitter of the internal master clock signal to less than a 300 ps rms time interval error (TIE). Even at these levels, extra noise or tones can appear in the DAC outputs if the jitter spectrum contains large spectral peaks. If the internal PLL is not used, it is best to use an independent crystal oscillator to generate the master clock.
PAGE 17
AD1937 SCK SDA 0 0 0 START BY MASTER (S) 0 1 ADDR1 R/W ADDR0 0 0 0 ACK. BY AD1937 (AS) FRAME 1 CHIP ADDRESS BYTE 0 0 1 1 0 ACK. BY MASTER (AM) FRAME 2 REGISTER ADDRESS BYTE SCK (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY MASTER (AM) FRAME 3 DATA BYTE TO AD1937 STOP BY MASTER (P) 07414-011 SDA (CONTINUED) Figure 13. I2C Write Format SCK 0 SDA 0 0 START BY MASTER (S) 0 1 ADDR1 ADDR0 R/W 0 0 ACK. BY AD1937 (AS) FRAME 1 CHIP ADDRESS BYTE 0 0 0 1 1 0 ACK.
PAGE 18
AD1937 Table 13. I2C Abbreviation Table Abbreviation S P AM AS Condition Repeated start by master Stop by master Acknowledge by master Acknowledge by AD1937 Table 14. Single Word I2C Write S Chip Address, R/W = 0 AS Register Address AS Data Word AS P Table 15. Burst Mode I2C Write S Chip Address, R/W = 0 AS Register Address AS Data Word 1 AS Data Word 2 AS Data Word N AS P Table 16.
PAGE 19
AD1937 24 bits by default and can be set to 16 or 20 bits in the DAC Control 2 and ADC Control 1 registers. The DAC serial formats are programmable in the DAC Control 0 register. The polarity of DBCLK and DLRCLK is programmable in the DAC Control 1 register. The ADC serial format is programmable in ADC Control 1 register. The ABCLK and ALRCLK clock polarities are programmed in ADC Control 2 register. In Figure 2, Figure 3, and Figure 15 all of the clocks are shown with their normal polarity.
PAGE 20
AD1937 The I/O pin functions of the serial ports are defined according to the serial mode that is selected. For a detailed description of the function of each pin in TDM and TDM/AUX modes, see Table 18. TIME-DIVISION MULTIPLEXED (TDM) MODES The serial ports of the AD1937 have several different TDM serial data modes. Single-line TDM mode is the most commonly used configuration (see Figure 16 and Figure 17).
PAGE 21
AD1937 ALRCLK ABCLK DSDATA1 (TDM DATA IN) UNUSED SLOTS EMPTY EMPTY EMPTY AUX DAC CHANNELS APPEAR AT AUX DAC PORTS 8 ON-CHIP DAC CHANNELS EMPTY DAC1L DAC1R DAC2L DAC2R DAC3L DAC3R DAC4L DAC4R AUX1L AUX1R AUX2L AUX2R 32 BITS MSB DLRCLK (AUX LRCLK IN/OUT) LEFT RIGHT ASDATA2 (AUX DAC1 DATA OUT) MSB MSB DSDATA4 (AUX DAC2 DATA OUT) MSB MSB 07414-015 DBCLK (AUX BCLK IN/OUT) Figure 18.
PAGE 22
AD1937 ALRCLK ABCLK ASDATA1 (TDM DATA OUT) 4 ON-CHIP ADC CHANNELS ADCL1 ADCR1 ADCL2 ADCR2 AUXILIARY ADC CHANNELS AUXL1 AUXR1 AUXL2 UNUSED SLOTS AUXR2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED 32 BITS MSB DLRCLK (AUX LRCLK IN/OUT) LEFT RIGHT DSDATA2 (AUX ADC1 DATA IN) MSB MSB DSDATA3 (AUX ADC2 DATA IN) MSB MSB 07414-017 DBCLK (AUX BCLK IN/OUT) Figure 20.
PAGE 23
AD1937 There are two configurations for the ADC port to work in daisy-chain mode. The first configuration is with an ABCLK at 256 × fS, see Figure 25. The second configuration is with an ABCLK at 512 × fS, see Figure 26. Note that in the 512 × fS ABCLK mode, the ADC channels occupy the first eight slots; the second eight slots are empty. The TDM ADC data in (ASDATA2) port of the first AD1937 must be grounded in all modes of operation.
PAGE 24
AD1937 DLRCLK DBCLK DSDATA1 DAC1L DAC1R DAC2L DAC2R DSDATA2 DAC3L DAC3R DAC4L DAC4L 07414-021 32 BITS MSB Figure 24.
PAGE 25
AD1937 Table 19.
PAGE 26
AD1937 ADDITIONAL MODES The AD1937 offers several additional modes for board level design enhancements. To reduce the EMI in board level design, serial data can be transmitted without an explicit BCLK. See Figure 28 and Figure 29 for an example of a DAC TDM data transmission mode that does not require high speed DBCLK. This configuration is applicable when the AD1937 master clock is generated by the PLL with the DLRCLK as the PLL reference frequency.
PAGE 27
AD1937 CONTROL REGISTERS DEFINITIONS The global address for the AD1937 is 0x08 OR’ed with ADDR1 and ADDR0 and one R/W bit; see Figure 13 and Figure 14. The address bits (Bits[18:17]) setting must correspond to the low/high state of Pin 30 and Pin 35. All registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register parameter is the default setting. Table 20.
PAGE 28
AD1937 Table 23. PLL and Clock Control 1 Register (Address 1, 0x01) Bit 0 1 2 3 7:4 Value 0 1 0 1 0 1 0 1 0000 Function PLL clock MCLK PLL clock MCLK Enabled Disabled Not locked Locked Reserved Description DAC clock source select ADC clock source select On-chip voltage reference PLL lock indicator (read-only) DAC CONTROL REGISTERS Table 24.
PAGE 29
AD1937 Table 25. DAC Control 1 Register (Address 3, 0x03) Bit 0 2:1 3 4 5 6 7 Value 0 1 00 01 10 11 0 1 0 1 0 1 0 1 0 1 Function Latch in midcycle (normal) Latch in at end of cycle (pipeline) 64 (2 channels) 128 (4 channels) 256 (8 channels) 512 (16 channels) Left low Left high Slave Master Slave Master DBCLK pin Internally generated Normal Inverted Description DBCLK active edge (TDM_IN) DBCLKs per frame DLRCLK polarity DLRCLK master/slave DBCLK master/slave DBCLK source DBCLK polarity Table 26.
PAGE 30
AD1937 Table 28. DACxx Volume Controls Registers (Address 6 to Address 13, 0x06 to 0x0D) Bit 7:0 Value 0 1 to 254 255 Function No attenuation −0.375 dB per step Full attenuation Description DAC volume control ADC CONTROL REGISTERS Table 29. ADC Control 0 Register (Address 14, 0x0E) Bit 0 1 2 3 4 5 7:6 Value 0 1 0 1 0 1 0 1 0 1 0 1 00 01 10 11 Function Normal Power down Off On Unmute Mute Unmute Mute Unmute Mute Unmute Mute 32 kHz/44.1 kHz/48 kHz 64 kHz/88.2 kHz/96 kHz 128 kHz/176.
PAGE 31
AD1937 Table 31. ADC Control 2 Register (Address 16, 0x10) Bit 0 1 2 3 5:4 6 7 Value 0 1 0 1 0 1 0 1 00 01 10 11 0 1 0 1 Function 50/50 (allows 32, 24, 20, or 16 BCLKs per channel) Pulse (32 BCLKs per channel) Drive out on falling edge (DEF) Drive out on rising edge Left low Left high Slave Master 64 cycles 128 cycles 256 cycles 512 cycles Slave Master ABCLK pin Internally generated Rev.
PAGE 32
AD1937 APPLICATIONS CIRCUITS Typical application circuits are shown in Figure 31 through Figure 34. Figure 31 shows a typical ADC input filter circuit. Recommended loop filters for LRCLK and MCLK as the PLL reference are shown in Figure 32. Output filters for the DAC outputs are shown in Figure 33 and a regulator circuit is shown in Figure 34. 120pF 5.76kΩ 5.76kΩ 2 100pF 3 – 1 OP275 + 68pF NPO 11kΩ 4.7µF 237Ω 5.76kΩ + 120pF DAC OUTN ADCxxN 1nF NPO 11kΩ 100pF 5 5.76kΩ – OP275 1nF NPO 4.
PAGE 33
AD1937 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 35.
PAGE 34
AD1937 NOTES Rev.
PAGE 35
AD1937 NOTES Rev.
PAGE 36
AD1937 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07414-0-6/10(B) Rev.