Datasheet

Data Sheet AD1933
Rev. E | Page 9 of 28
Pin No. Input/Output Mnemonic Description
23 I VSUPPLY 5 V Input to Regulator, Emitter of Pass Transistor.
24 I VSENSE 3.3 V Output of Regulator, Collector of Pass Transistor.
25 O VDRIVE Drive for Base of Pass Transistor.
26 O AUXDATA1 AUX DAC1 data out (to external DAC1).
27, 49, 50,
63, 64
NC
No Connect.
28 I/O AUXTDMBCLK Auxiliary Mode Only DAC TDM Bit Clock.
29 I/O AUXTDMLRCLK Auxiliary Mode Only DAC LR TDM Clock.
30 I CIN Control Data Input (SPI).
31 I/O COUT Control Data Output (SPI).
32
I
DVDD
Digital Power Supply. Connect to digital 3.3 V supply.
33 I DGND Digital Ground.
34 I CCLK Control Clock Input (SPI).
35 I
CLATCH
Latch Input for Control Data (SPI).
36 O OL1P DAC 1 Left Positive Output.
37 O OL1N DAC 1 Left Negative Output.
38 O OR1P DAC 1 Right Positive Output.
39 O OR1N DAC 1 Right Negative Output.
40 O OL2P DAC 2 Left Positive Output.
41 O OL2N DAC 2 Left Negative Output.
42 O OR2P DAC 2 Right Positive Output.
43
O
OR2N
DAC 2 Right Negative Output.
44 I AGND Analog Ground.
45 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.
46 I AGND Analog Ground.
47 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
48 I AGND Analog Ground.
51 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.
52 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 µF||100 nF
to AGND.
53 to 60 I NC Must Be Tied to Common Mode, Pin 52. Alternately, ac-couple these pins to ground.
61 O LF PLL Loop Filter, Return to AVDD.
62
I
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.