REV. A
AD1896
–4–
TIMING DIAGRAMS
t
LRIS
t
SIH
t
DIS
t
SIL
t
DIH
t
LROS
t
SOH
t
DOPD
t
SOL
t
DOH
t
LROH
t
TDMS
t
TDMH
LRCLK_I
SCLK
I
SDATA I
LRCLK
O
SCLK
O
SDATA
O
LRCLK
O
SCLK
O
TDM
IN
Figure 1. Input and Output Serial Port Timing (SCLK I/O,
LRCLK I/O, SDATA I/O, TDM_IN)
t
RSTL
MCLK I
RESET
Figure 2.
RESET
Timing
t
MPWH
t
MPWL
Figure 3. MCLK_I Timing
