Datasheet

REV. A
–3–
AD1896
DIGITAL TIMING (–40C < T
A
< +105C, VDD_CORE = 3.3 V  5%, VDD_IO = 5.0 V  10%)
Parameter
1
Min Typ Max Unit
t
MCLKI
MCLK_I Period 33.3 ns
f
MCLK
MCLK_I Frequency 30.0
2, 3
MHz
t
MPWH
MCLK_I Pulsewidth High 9 ns
t
MPWL
MCLK_I Pulsewidth Low 12 ns
Input Serial Port Timing
t
LRIS
LRCLK_I Setup to SCLK_I 8 ns
t
SIH
SCLK_I Pulsewidth High 8 ns
t
SIL
SCLK_I Pulsewidth Low 8 ns
t
DIS
SDATA_I Setup to SCLK_I Rising Edge 8 ns
t
DIH
SDATA_I Hold from SCLK_I Rising Edge 3 ns
Propagation Delay from MCLK_I Rising Edge to SCLK_I Rising Edge
(Serial Input Port MASTER) 12 ns
Propagation Delay from MCLK_I Rising Edge to LRCLK_I Rising Edge
(Serial Input Port MASTER) 12 ns
Output Serial Port Timing
t
TDMS
TDM_IN Setup to SCLK_O Falling Edge 3 ns
t
TDMH
TDM_IN Hold from SCLK_O Falling Edge 3 ns
t
DOPD
SDATA_O Propagation Delay from SCLK_O, LRCLK_O 20 ns
t
DOH
SDATA_O Hold from SCLK_O 3 ns
t
LROS
LRCLK_O Setup to SCLK_O (TDM Mode Only) 5 ns
t
LROH
LRCLK_O Hold from SCLK_O (TDM Mode Only) 3 ns
t
SOH
SCLK_O Pulsewidth High 10 ns
t
SOL
SCLK_O Pulsewidth Low 5 ns
t
RSTL
RESET Pulsewidth Low 200 ns
Propagation Delay from MCLK_I Rising Edge to SCLK_O Rising Edge
(Serial Output Port MASTER) 12 ns
Propagation Delay from MCLK_I Rising Edge to LRCLK_O Rising Edge
(Serial Output Port MASTER) 12 ns
NOTES
1
Refer to Timing Diagrams section.
2
The maximum possible sample rate is: FS
MAX
= f
MCLK
/138.
3
f
MCLK
of up to 34 MHz is possible under the following conditions: 0∞C < T
A
< 70∞C, 45/55 or better MCLK_I duty cycle.
Specifications subject to change without notice.