Datasheet

REV. A
AD1896
–24–
Serial Data Port Master Clock Modes
Either of the AD1896 serial ports can be configured as a master
serial data port. However, only one serial port can be a master
while the other has to be a slave. In master mode, the AD1896
requires a 256 ¥ f
S
, 512 ¥ f
S
, or 768 ¥ f
S
master clock (MCLK_I).
For a maximum master clock frequency of 30 MHz, the maxi-
mum sample rate is limited to 96 kHz. In slave mode, sample
rates up to 192 kHz can be handled.
When either of the serial ports is operated in master mode, the
master clock is divided down to derive the associated left/
right subframe clock (LRCLK) and serial bit clock (SCLK).
The master clock frequency can be selected for 256, 512, or 768
times the input or output sample rate. Both the input and out-
put serial ports will support master mode LRCLK and SCLK
generation for all serial modes, left justified, I
2
S, right justified, and
TDM for the output serial port.
Table IV. Serial Data Port Clock Modes
MMODE_0/
MMODE_1/
MMODE_2
Interface Format
210
000Both serial ports are in slave mode.
001Output serial port is master with 768 ¥ f
S_OUT
.
010Output serial port is master with 512 ¥ f
S_OUT
.
011Output serial port is master with 256 ¥ f
S_OUT
.
100Matched-phase Mode
101Input serial port is master with 768 ¥ f
S_IN
.
110Input serial port is master with 512 ¥ f
S_IN
.
111Input serial port is master with 256 ¥ f
S_IN
.
AD1896
TDM_IN
SDATA_O
LRCLK_O
CLOCK-MASTER
AND
PHASE-MASTER
M1 M2 M0
1 0 1
SCLK_O
SHARC
DSP
DR0
RFS0
RCLK0
SLAVE-1
SLAVE-n
STANDARD MODE
MATCHED-PHASE MODE
AD1896
TDM_IN
SDATA_O
LRCLK_O
M1 M2 M0
0 0 0
0 1 0
SCLK_O
AD1896
TDM_IN
SDATA_O
LRCLK_O
M1 M2 M0
SCLK_O
0 0 0
0 1 0
Figure 12. Daisy-Chain Configuration for TDM Mode (First AD1896 Being Clock-Master)
MATCHED-PHASE MODE (NON-TDM MODE) APPLICATION
AD1896
SLAVE1
M2 M1 M0
AD1896
TDM_IN
SDATA_I
LRCLK_I
SCLK_I
MCLK
RESET
SDATA_O
LRCLK_O
SCLK_O
PHASE-MASTER
M2 M1 M0
AD1896
SLAVE2
M2 M1 M0
AD1896
SLAVEn
M2 M1 M0
0 0 0
1 0 0
1 0 0
1 0 0
LRCLK
I
(f
S_IN
)
SCLK
I
LRCLK
O
(f
S_OUT
)
SCLK
O
(64f
S_OUT
)
MCLK
RESET
SDOm
SDO1
SDO2
SDOn
TDM_IN
SDATA_I
LRCLK_I
SCLK_I
MCLK
RESET
SDATA_O
LRCLK_O
SCLK_O
TDM_IN
SDATA_I
LRCLK_I
SCLK_I
MCLK
RESET
SDATA_O
LRCLK_O
SCLK_O
TDM_IN
SDATA_I
LRCLK_I
SCLK_I
MCLK
RESET
SDATA_O
LRCLK_O
SCLK_O
Figure 13. Typical Configuration for Matched-Phase Mode Operation