AD1877
REV. A
–17–
WCLK
INPUT
DATA & TAG
OUTPUTS
XMIT SAMPLE SAMPLE
t
BPWL
t
BPWH
t
BPWH
t
BPWL
t
DLYLRDT
MSB MSB-1
t
DLYBDT
t
SETLRBS
BCLK INPUT
RDEDGE = LO
BCLK OUTPUT
RDEDGE = HI
LRCK
INPUT
XMIT
t
SETWBS
Figure 18. Slave Mode Clock Timing
CLKIN INPUT
RESET INPUT
t
CPWH
t
CPWL
t
CLKIN
t
RPWL
Figure 19. CLKIN and
RESET
Timing
