Datasheet

AD1877
REV. A
–16–
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
31 32 1 2 3 4 16
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
19 20 21 32 1 2
INPUT
HI HI
51718
LSB
LEFT TAG
MSB LSB
RIGHT TAG LEFT TAG
LSB
MSB-14
LSB
PREVIOUS DATA
MSB-1 MSB-2 MSB-3
LEFT DATA
MSB-4 MSB-3 MSB-4
LSB
MSB-1 MSB-2
RIGHT DATA
LSB
MSB-1
LEFT DATA
LRCK
INPUT
MSB
MSB
MSB MSB
MSB
Figure 15. Serial Data Output Timing: Slave Mode, Left-Justified with No MSB Delay,
32-Bit Frame Mode, S/
M = Hl, R L JUST = LO, MSBDLY = Hl
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
32 1 2 3 4 5 17
SOUT
OUTPUT
TAG
OUTPUT
20 21 22 1 2 3
INPUT
WCLK
OUTPUT
HI HI
61819
MSB
LEFT TAG
MSB LSB
RIGHT TAG
MSB-14
LSB
PREVIOUS DATA
MSB-1 MSB-2 MSB-3
LEFT DATA
MSB-4 MSB-3 MSB-4
LSB
MSB-1 MSB-2
RIGHT DATA
LSB
MSB-1
LEFT DATA
MSB
LEFT TAG
MSB
RIGHT TAG
LRCK
INPUT
MSB
LSB
MSB MSB
LSB
Figure 16. Serial Data Output Timing: Slave Mode, I
2
S-Justified, 32-Bit Frame Mode,
S/
M = Hl, R L JUST= LO, MSBDLY = LO
BCLK OUTPUT (64 x F
S
)
RDEDGE = LO
CLKIN
INPUT
BCLK OUTPUT (64 x F
S
)
RDEDGE = HI
WCLK
OUTPUT
DATA & TAG
OUTPUTS
XMIT XMITXMIT XMIT
t
DLYCKB
t
BPWL
t
BPWH
t
BPWL
t
BPWH
t
DLYBLR
t
DLYDT
t
DLYBWR
t
DLYBWF
LRCK
OUTPUT
Figure 17. Master Mode Clock Timing