Datasheet

AD1877
REV. A
–15–
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
32 1 2 16 17 18 19 1 2 16 17 18 19 20 1 2
MSB-14 LSB
PREVIOUS DATA
MSB-1
LEFT DATA
MSB-2
LSB
RIGHT DATA
SOUT
OUTPUT
ZEROS ZEROS
MSB-1 MSB-2
LSB
ZEROS
WCLK
OUTPUT
TAG
OUTPUT
MSB LSB
LEFT TAG
MSB LSB
RIGHT TAG
20
LRCK
OUTPUT
OUTPUT
MSB MSB
Figure 12. Serial Data Output Timing. Master Mode, Right-Justified with MSB Delay,
WCLK Pulsed in 17th BCLK Cycle, S/
M = LO, R L JUST = Hl, MSBDLY = LO
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
31 32 1 2 3 16
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
LSB
LEFT TAG
LSB
RIGHT TAG
31 32 1 2 3 16
MSB-1
LEFT DATA
MSB-2
LSB
MSB-1
RIGHT DATA
MSB-2
LSB
ZEROSZEROS ZEROS
LRCK
OUTPUT
OUTPUT 17 1817 18
MSB
MSB
MSB
MSB
Figure 13. Serial Data Output Timing: Master Mode, Left-Justified with No MSB Delay,
S/
M = LO, R L JUST = LO, MSBDLY = Hl
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
321234 17
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
MSB
LEFT TAG
MSB
RIGHT TAG
31 32 1 2 3 4 17
MSB-1
LEFT DATA
MSB-2
LSB
MSB-1
RIGHT DATA
MSB-2
LSB
ZEROSZEROS ZEROS
OUTPUT
LRCK
OUTPUT
MSB
LSB
MSB
LSB
Figure 14. Serial Data Output Timing: Master Mode, I
2
S-Justified, S/ M = LO, R L JUST = LO,
MSBDLY = LO