Datasheet

AD1877
REV. A
–13–
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
31 32 1 2 15 16 17 18 19 32 1 2 15 16 17 18 19 32 1 2
MSB-14 LSB
PREVIOUS DATA
MSB-1
LEFT DATA
MSB-2
LSB
RIGHT DATA
SOUT
OUTPUT
ZEROS
ZEROS
MSB-1 MSB-2
LSB
ZEROS
WCLK
OUTPUT
TAG
OUTPUT
MSB LSB
LEFT TAG
MSB LSB
RIGHT TAG
MSB LSB
LEFT TAG
LRCK
INPUT
INPUT
MSB MSB
Figure 7. Serial Data Output Timing: Slave Mode, Right-Justified with No MSB Delay,
S/M = Hl, RLJUST = Hl, MSBDLY = Hl
BCLK
RDEDGE= LO
BCLK
RDEDGE = HI
MSB-1
LEFT DATA
MSB-2
LSB
SOUT
OUTPUT
ZEROS
RIGHT DATA
MSB-1 MSB-2
LSB
ZEROS
WCLK
INPUT
TAG
OUTPUT
MSB
LEFT TAG
MSB
RIGHT TAG
ZEROS
1234 17 1234 17
INPUT
LRCK
INPUT
MSB
LSB
MSB
LSB
Figure 8. Serial Data Output Timing: Slave Mode, Data Position Controlled by WCLK Input,
S/
M = Hl, R L JUST= Hl, MSBDLY = LO
dBFS
0
–80
1.0
–60
–70
0.10.0
–40
–50
–30
–20
–10
0.90.80.70.60.50.40.30.2
–110
–90
–100
NORMALIZED F
S
TPC 7. Digital Filter Signal Transfer Function to F
S