Datasheet

AD1854
–9–REV. A
t
DLS
BCLK
L/RCLK
SDATA
LEFT-JUSTIFIED
MODE
SDATA
RIGHT-JUSTIFIED
MODE
LSB
SDATA
I
2
S-JUSTIFIED
MODE
t
DBH
t
DBP
t
DBL
t
DDS
MSB
MSB-1
t
DDH
t
DDS
MSB
t
DDH
t
DDS
t
DDS
t
DDH
t
DDH
MSB
Figure 9. Serial Data Port Timing
BCLK
L/RCLK
SDATA
LEFT-JUSTIFIED
DSP SERIAL
PORT STYLE MODE
MSB-1
t
DBH
t
DBP
t
DBL
t
DLS
t
DLH
t
DDS
t
DDH
MSB
Figure 10. Serial Data Port Timing–DSP Serial Port Style Mode
PD/RST
MCLK
t
PDRP
t
DMP
t
DMH
t
DML
Figure 11. Power-Down/Reset Timing
Timing Diagrams
The serial data port timing is shown in Figures 9 and 10. The
minimum bit clock HI pulsewidth is t
DBH
and the minimum bit
clock LO pulsewidth is t
DBL
. The minimum bit clock period is
t
DBP
. The left/right clock minimum setup time is t
DLS
and the
left/right clock minimum hold time is t
DLH
. The serial data
minimum setup time is t
DDS
and the minimum serial data hold
time is t
DDH
.
The power-down/reset timing is shown in Figure 11. The mini-
mum reset LO pulse width is t
PDRP
(four MCLK periods) to
accomplish a successful AD1854 reset operation.