Datasheet

AD1852
Rev. A | Page 5 of 20
DIGITAL TIMING
Guaranteed over 0°C to 70°C, AVDD = DVDD = 5.0 V × 10%.
Table 8.
Parameter Description Min Unit
t
DMP
MCLK period (f
MCLK
= 256 × f
LRCLK
)
1
54 ns
t
DML
MCLK low pulse width (all modes) 0.4 × t
DMP
ns
t
DMH
MCLK high pulse width (all modes) 0.4 × t
DMP
ns
t
DBH
BCLK high pulse width (see Figure 26) 20 ns
t
DBL
BCLK low pulse width (see Figure 26) 20 ns
t
DBP
BCLK period (see Figure 26) 60 ns
t
DLS
LRCLK setup (see Figure 26) 20 ns
t
DLH
LRCLK hold (DSP serial port mode only) 5 ns
t
DDS
SDATA setup (see Figure 26) 5 ns
t
DDH
SDATA hold (see Figure 26) 10 ns
t
RSTL
RESET
low pulse width
15
ns
1
Higher MCLK frequencies are allowable when using the on-chip master clock autodivide feature.