Datasheet

AD1852
Rev. A | Page 13 of 20
BCLK
LRCLK
SDATA
LEFT-JUSTIFIED
MODE
SDATA
I
2
C-JUSTIFIED
MODE
SDATA
RIGHT-JUSTIFIED
MODE
LSB
t
DBH
t
DBP
t
DBL
t
DLS
t
DDS
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
MSB
MSB – 1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
08457-026
Figure 26. Serial Data Port Timing
Table 13. Allowable MCLK Frequencies and Internal Delta Clock Rates
Chip Mode Allowable Master Clock Frequencies Nominal Input Sample Rate (kHz) Internal Sigma-Delta Clock Rate
INT 8× Mode 256 × f
S
, 384 × f
S
, 512 × f
S
, 768 × f
S
, 1024 × f
S
48 128 × f
S
INT 4× Mode 128 × f
S
, 192 × f
S
, 256 × f
S
, 384 × f
S
, 512 × f
S
96 64 × f
S
INT 2× Mode 64 × f
S
, 96 × f
S
, 128 × f
S
, 192 × f
S
, 256 × f
S
192 32 × f
S
D15
D14
D0
t
CHD
t
CLH
t
CLL
t
CLSU
t
CCL
t
CCH
t
CSU
CDATA
CCLK
CLATCH
0
8457-027
Figure 27. Serial Control Port Timing
MASTER CLOCK AUTODIVIDE FEATURE
The AD1852 has a circuit that autodetects the relationship between
the master clock and the incoming serial data and internally sets
the correct divide ratio to run the interpolator and modulator. The
allowable frequencies for each mode are shown in Table 13.
Master clock should be synchronized with LRCLK; however,
phase relation between master clock and LRCLK is not critical.
SPI REGISTER DEFINITIONS
The SPI port allows flexible control of many chip parameters. It
is organized around three registers: a left-channel volume register, a
right-channel volume register, and a control register. Each write
operation to the AD1852 SPI control port requires 16 bits of
serial data in MSB-first format. The bottom two bits are used to
select one of three registers, and the top 14 bits are then written
to that register. This allows a write to one of the three registers
in a single 16-bit transaction.
The SPI CCLK signal is used to clock in the data. The incoming
data should change on the falling edge of this signal. At the end
of the 16 CCLK periods, the CLATCH signal should rise to
clock the data internally into the AD1852.
The serial control port timing is shown in Figure 27, and the
SPI digital timing values are listed in Table 14.
Table 14. SPI Digital Timing
Parameter Description Value
t
CCH
CCLK high pulse width 40 ns
t
CCL
CCLK low pulse width 40 ns
t
CSU
CDATA setup time 10 ns
t
CHD
CDATA hold time 10 ns
t
CLL
CLATCH low pulse width 10 ns
t
CLH
CLATCH high pulse width 10 ns
t
CLSU
CLATCH setup time 4 × t
MCLK