Datasheet

Data Sheet AD1836A
Rev. A | Page 21 of 24
Table 19. ADC Control Register 3
When changing clock mode, other SPI bits that are written during the same SPI transaction may be lost. Therefore, it is recommended
that these be set separately.
Address
RD/WR
Reserved
Clock Mode
Function
Left Differential
I/P Select
Right
Differential
I/P Select
Left
MUX/PGA
Enable
Left MUX
I/P Select
Right
MUX/PGA
Enable
Right
MUX I/P
Select
15, 14,
13, 12
11 10, 9, 8 7, 6 5 4 3 2 1 0
1110 0 000 00 = 256 × f
S
01 = 512 × f
S
10 = 768 × f
S
0 = Differential
PGA Mode
1 = PGA/MUX
Mode (Single-
Ended Input)
0 = Differential
PGA Mode
1 = PGA/MUX
Mode (Single-
Ended Input)
0 = Direct
1 = MUX/PGA
0 = I/P 0
1 = I/P 1
0 = Direct
1 = MUX/PGA
0 = I/P 0
1 = I/P 1
Table 20. ADC Peak Level Data Registers
Address RD/WR Reserved
Peak Level Data (10 Bits)
6 Data Bits 4 Fixed Bits
15, 14, 13, 12 11 10 9:4 3:0
1000 = ADC1L
1001 = ADC1R
1010 = ADC2L
1011 = ADC2R
1 0 000000 = 0.0 dBFS
000001 = –1.0 dBFS
000010 = –2.0 dBFS
000011 = –3.0 dBFS
111100 = –60 dBFS Min
0000
The 4 LSBs are always zero.