Datasheet

Data Sheet AD1836A
Rev. A | Page 15 of 24
LRCLK
BCLK
DATA
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
RIGHT 0
SLOT 4
RIGHT 1
MSB MSB–1 MSB–2
LRCLK
BCLK
DATA
32 BCLKs
128 BCLKs
Figure 5. ADC Packed Mode 128
LRCLK
BCLK
DATA
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 5
RIGHT 0
SLOT 6
RIGHT 1
32 BCLKs
MSB MSB–1 MSB–2
256 BCLKs
SLOT 3 SLOT 4 SLOT 7 SLOT 8
LRCLK
BCLK
DATA
Figure 6. ADC Packed Mode 256
LRCLK
BCLK
DATA
SLOT 1
LEFT 0
SLOT 2
LEFT 1
MSB MSB–1 MSB–2
20 BCLKs
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 3
LEFT 2
SLOT 6
RIGHT 2
LRCLK
BCLK
DATA
128 BCLKs
Figure 7. DAC Packed Mode 128
LRCLK
BCLK
DATA
SLOT 1
LEFT 0
SLOT 2
LEFT 1
MSB MSB–1 MSB–2
32 BCLKs
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 3
LEFT 2
SLOT 6
RIGHT 2
LRCLK
BCLK
DATA
256 BCLKs
Figure 8. DAC Packed Mode 256