Datasheet

REV. A
AD1835A
–5–
Parameter Min Max Unit Comments
TDM256 MODE (Master, 48 kHz and 96 kHz)
t
TBD
BCLK Delay 40 ns From MCLK Rising
t
FSD
FSTDM Delay 5 ns From BCLK Rising
t
TABDD
ASDATA Delay 10 ns From BCLK Rising
t
TDDS
DSDATA1 Setup 15 ns To BCLK Falling
t
TDDH
DSDATA1 Hold 15 ns From BCLK Falling
TDM256 MODE (Slave, 48 kHz and 96 kHz)
f
AB
BCLK Frequency 256 ⫻ f
S
t
TBCH
BCLK High 17 ns
t
TBCL
BCLK Low 17 ns
t
TFS
FSTDM Setup 10 ns To BCLK Falling
t
TFH
FSTDM Hold 10 ns From BCLK Falling
t
TBDD
ASDATA Delay 15 ns From BCLK Rising
t
TDDS
DSDATA1 Setup 15 ns To BCLK Falling
t
TDDH
DSDATA1 Hold 15 ns From BCLK Falling
TDM512 MODE (Master, 48 kHz)
t
TBD
BCLK Delay 40 ns From MCLK Rising
t
FSD
FSTDM Delay 5 ns From BCLK Rising
t
TABDD
ASDATA Delay 10 ns From BCLK Rising
t
TDDS
DSDATA1 Setup 15 ns To BCLK Falling
t
TDDH
DSDATA1 Hold 15 ns From BCLK Falling
TDM512 MODE (Slave, 48 kHz )
f
AB
BCLK Frequency 512 ⫻ f
S
t
TBCH
BCLK High 17 ns
t
TBCL
BCLK Low 17 ns
t
TFS
FSTDM Setup 10 ns To BCLK Falling
t
TFH
FSTDM Hold 10 ns From BCLK Falling
t
TBDD
ASDATA Delay 15 ns From BCLK Rising
t
TDDS
DSDATA1 Setup 15 ns To BCLK Falling
t
TDDH
DSDATA1 Hold 15 ns From BCLK Falling
AUXILIARY INTERFACE (48 kHz and 96 kHz)
t
AXDS
AAUXDATA Setup 10 ns To AUXBCLK Rising
t
AXDH
AAUXDATA Hold 10 ns From AUXBCLK Rising
f
ABP
AUXBCLK Frequency 64 ⫻ f
S
Slave Mode
t
AXBH
AUXBCLK High 15 ns
t
AXBL
AUXBCLK Low 15 ns
t
AXLS
AUXLRCLK Setup 10 ns To AUXBCLK Rising
t
AXLH
AUXLRCLK Hold 10 ns From AUXBCLK Rising
Master Mode
t
AUXLRCLK
AUXLRCLK Delay 15 ns From AUXBCLK Falling
t
AUXBCLK
AUXBCLK Delay 20 ns From MCLK Rising
Specifications subject to change without notice.
MCLK
t
MH
P
D/RST
t
ML
t
PDR
t
MCLK
Figure 1. MCLK and PD / RST Timing