Datasheet

REV. A–4–
AD1835A
TIMING SPECIFICATIONS
Parameter Min Max Unit Comments
MASTER CLOCK AND RESET
t
MH
MCLK High 15 ns
t
ML
MCLK Low 15 ns
t
PDR
PD/RST Low 20 ns
SPI
®
PORT
t
CCH
CCLK High 40 ns
t
CCL
CCLK Low 40 ns
t
CCP
CCLK Period 80 ns
t
CDS
CDATA Setup 10 ns To CCLK Rising
t
CDH
CDATA Hold 10 ns From CCLK Rising
t
CLS
CLATCH Setup 10 ns To CCLK Rising
t
CLH
CLATCH Hold 10 ns From CCLK Rising
t
COE
COUT Enable 15 ns From CLATCH Falling
t
COD
COUT Delay 20 ns From CCLK Falling
t
COTS
COUT Three-State 25 ns From CLATCH Rising
DAC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Slave)
t
DBH
DBCLK High 60 ns
t
DBL
DBCLK Low 60 ns
f
DB
DBCLK Frequency 64 ⫻ f
S
t
DLS
DLRCLK Setup 10 ns To DBCLK Rising
t
DLH
DLRCLK Hold 10 ns From DBCLK Rising
t
DDS
DSDATA Setup 10 ns To DBCLK Rising
t
DDH
DSDATA Hold 10 ns From DBCLK Rising
Packed 128/256 Modes (Slave)
t
DBH
DBCLK High 15 ns
t
DBL
DBCLK Low 15 ns
f
DB
DBCLK Frequency 256 ⫻ f
S
t
DLS
DLRCLK Setup 10 ns To DBCLK Rising
t
DLH
DLRCLK Hold 10 ns From DBCLK Rising
t
DDS
DSDATA Setup 10 ns To DBCLK Rising
t
DDH
DSDATA Delay 10 ns From DBCLK Rising
ADC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Master)
t
ABD
ABCLK Delay 25 ns From MCLK Rising Edge
t
ALD
ALRCLK Delay Low 5 ns From ABCLK Falling Edge
t
ABDD
ASDATA Delay 10 ns From ABCLK Falling Edge
Normal Mode (Slave)
t
ABH
ABCLK High 60 ns
t
ABL
ABCLK Low 60 ns
f
AB
ABCLK Frequency 64 ⫻ f
S
t
ALS
ALRCLK Setup 5 ns To ABCLK Rising
t
ALH
ALRCLK Hold 15 ns From ABCLK Rising
t
ABDD
ASDATA Delay 15 ns From ABCLK Falling Edge
Packed 128/256 Mode (Master)
t
PABD
ABCLK Delay 40 ns From MCLK Rising Edge
t
PALD
LRCLK Delay 5 ns From ABCLK Falling Edge
t
PABDD
ASDATA Delay 10 ns From ABCLK Falling Edge