KING FHAD UNIVERSITY OF PETROLEUM & MINERALS Collage of Computer Sciences & Engineering Department of Computer Engineering COE305 Microcomputer Systems Design Lab Manual
COE305 LAB MANUAL Microcomputer Systems Design by Dr. Abdul Rahim Naseer Mr. Khaled Al-Utaibi Mr.
Table of Contents Design & Fabrication of an 8086 Microprocessor System Interfacing the Clock Generator to the CPU 2 Designing the Bus System 5 Designing the Memory System 8 Interfacing I/O Ports 12 Testing the 80806 Microcomputer System 15 Interface Experiments Using 8086 Microprocessor Kits & Application Boards Flight 8086 Training Board 21 Conducting Simple I/O Operations Using Flight 86 Training Kit 30 Generating Timing Sequences 37 Analog To Digital & Digital
C O E 3 0 5 L A B 1 Part M A N U A L Design & Fabrication of an 8086 Microprocessor System I n this part of the lab, the students are required to design and fabricate an 8086 based microcomputer system. The lab experiments in this part, consist of designing, assembling and testing of the fabricated system. The design, assembling and testing will be carried out by the students in an incremental manner as indicated below. 1. Connecting and testing clock driver circuit with microprocessor. 2.
C O E 3 0 5 L A B 1 Experiment M A N U A L Interfacing the Clock Generator to the CPU 1.1 Background The 8086 CPU has 16 data lines and 20 address lines. The CPU uses time multiplexing for the Address, data, and some status lines. The Clock Generator and Driver 8284 is a device capable of providing the CPU with Clock, reset logic, and ready logic. For this it uses a crystal oscillator that must be 3 times the frequency of the CPU (15 MHz Crystal). 1.
C O E 3 0 5 L A B M A N U A L 1 Capacitor (10u), and Oscilloscope 1.4 Procedure 1. Make a short review of the clock generator 8284 (Appendix II) and identify the three major functions that this device can operate. Figure 1.1: Top view of the 8284 clock generator 2. Implement the design shown in Figure 1.2 and check the output signal at CLK, PCLK, and OSC using the oscilloscope. Interface the CLK line to CPU and show your instructor the resulting signals. Figure 1.
C O E 3 0 5 L A B M A N U A L Figure 1.3: Reset Circuit 4. Read pin description of the 8086 microprocessor (Appendix), and determine what should be connected to the following pins (assume minimum mode): a. MN / MX (pin 33) b. HOLD (pin 31) c. TEST (pin 23) d. READY (pin 22) e. RESET (pin 21) f. CLK (pin 19) g. INTR (pin 18) h. NMI (pin 17) 5. Connect VCC and GND pins of the 8086 microprocessor and test the ALE signal (pin 25) using the oscilloscope. Exercises 1.1.
C O E 3 0 5 L A B 2 Experiment M A N U A L Designing the Bus System 2.1 Background The 8086 CPU has 16 data lines and 20 address lines. The CPU uses time multiplexing for the address, data, and some status lines. The CPU generates the addresses A0-A15 on lines AD0- AD15 and A16-A19 on lines AS16-AS19 during clock T1. This event is indicated by a bus control signal ALE. During T2, T3, and T4 the CPU uses the AD0AD15 to transfer data, i.e. as data bus.
C O E 3 0 5 L A B M A N U A L 2.4 Procedure 1. Review the function of the 74LS373 octal latch (Appendix). Identify its input and output lines as well as the control signals available on this chip. 2. Each group discuss and give solutions to the following issues: a. What are the AD and AS lines that must be demultiplexed? b. The number of needed octal latches. c. What should be connected to control lines of the 74LS373 octal latch (i.e. G and OC). 3.
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C O E 3 0 5 L A B 3 Experiment M A N U A L Designing the Memory System 3.1 Background The 8086 CPU has addressing capability of 1 Mega Bytes as well as a 16-bit data bus. Basically, EPROM and SRAM memory chips are byte organized. The 8086 CPU requires that the memory be organized as two banks called the even and odd banks. The EPROM memory is to store resident programs that must run when the microprocessor system is powered on.
C O E 3 0 5 L A B M A N U A L Two 8 Kbytes SRAM memories (6264), and Two 8 Kbytes EPROM memories (2764) 3.4 Procedure In this project, each group will design a memory system consisting of two memory modules. The first is a 16 KByte SRAM starting at address 00000h. The second is a 16 KByte EPROM ending at address FFFFh (Why?). Refer to your text book for more details about memory system design. 1. Each group discuss and answer the following issues: a.
C O E 3 0 5 L A B M A N U A L 3. Implement the decoder shown in Figure 3.1 which takes as input RD , WR and M / IO , and produces memory read ( MEMR ), memory write ( MEMW ), I/O read ( IOR ) and I/O write ( IOW ) signals. 4. After completing the wiring, each group must carry out visual and electrical testing of the connections (e.g. using multimeters) as well as doing necessary corrections. Figure 3.1: Generating the four memory and I/O control bus signals from the 8086's RD, WR and I/O signals.
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C O E 3 0 5 L A B 4 Experiment M A N U A L Interfacing I/O Ports 4.1 Background The I/O ports are very essential in any computer system because they enable the user to communicate with the system. In this experiment, we will design and implement a very simple form of I/O ports (switches for input and LEDs for output). The input port should be designed to pass the data on the input switches to the data bus if and only if an input instruction (I/O read cycle) is executed by the CPU.
C O E 3 0 5 L A B M A N U A L TTL 74LS373 octal latch, 8 Switches, 8 LEDs, and 8 resisters 4.4 Procedure 1. The lab instructor should explain how to connect the switches and LEDs to the system 2. Each group should draw a complete circuit diagram of the input port using 74LS245 that shows what should be connected to its inputs, outputs and control lines. 3.
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C O E 3 0 5 L A B 5 Experiment M A N U A L Testing the 80806 Microcomputer System 5.1 Introduction By this experiment your system should include the following: 1. an 8086 microprocessor, 2. a clock generator with 15MHz crystal, 3. a fully demultiplexed bus system (74LS373 octal latches), 4. a memory system including two SRAM memory chips and two EPROM memory chips each of size 8Kbytes, 5. decoders, and 6.
C O E 3 0 5 L A B M A N U A L 5.2 Equipment Use of a prototype-board that already includes an 8086 CPU operating in minimum mode with clock generator and a fully demultiplexed data and address buses in addition to two 8 Kbytes SRAM memories (6264) and two 8 Kbytes EPROM memories (2764), MS-DOS Debugger, EPROM Eraser, EPROM Programmer, Oscilloscope, Logic Probe, and Multimeter 5.3 Procedure 1.
C O E 3 0 5 L A B M A N U A L C:\> Debug -a 0000:0000 0000:0000 MOV AL, 1 0000:0002 MOV CX, FFFF 0000:0005 OUT 0, AL 0000:0007 LOOP 0005 0000:0009 ROL AL, 0000:000B JMP 0002 1 0000:000D -u 0000:0000 0000:0000 B001 MOV AL, 1 0000:0002 B9FFFF MOV CX, FFFF 0000:0005 E600 OUT 0, AL 0000:0007 E2FC LOOP 0005 0000:0009 D0C0 ROL AL, 0000:000B EBF5 JMP 0002 . . . . . . Relative Address Machine Code 1 Assembly Code Figure 5.
C O E 3 0 5 L A B M A N U A L 5.4 Debugging the System In case that your system is not functioning, you can carry out hardware testing of the microcomputer system through general inspection and hardware debugging as explained in the following steps: Step 1: Visual inspection and testing: 1. Make sure that the VCC and GND you are using are appropriate. Use oscilloscope to measure VCC on your system. 2. Identify the VCC and GND lines on your board and make sure all chips receive them on the right pins.
C O E 3 0 5 L A B M A N U A L I/O write cycles are observed in the right order. For this test we have to follow the steps below: 1. Analyze the program and find out the expected chip-select pattern on the EPROM and I/O write cycles. 2. Turn on your microprocessor system, and use the oscilloscope to check memory and I/O read signals (i.e., chip-select of the EPROMs and latch-enable of the I/O port). 3. If you do not see the expected pattern, then there is still a problem with your system.
C O E 3 0 5 L A B 2 Part M A N U A L Interface Experiments using 8086 Microprocessor Kits & Application Boards I In this part, students will be carrying out interfacing experiments using 8086 microprocessor kits and interfacing boards. These kits need to be interfaced to the PCs for downloading programs.
C O E 3 0 5 L A B 1 Experiment M A N U A L Flight 8086 Training Board Objective The aim of this lab experiment is to familiarize the students with Flight 8086 training board. Equipment Flight 8086 training board, PC with Flight86 software, download cable.
C O E 3 0 5 L A B M A N U A L 1.1 Background The FLIGHT 86 Trainer System is designed to simplify the teaching of the 8086 CPU and some of its commonly used peripherals. It can be linked to most PCs with a simple serial line, so that code may be assembled and debugged in a supportive software environment before being downloaded into the RAM on the board. The board itself may then be linked to other peripheral devices. A block diagram of this mode of operation is shown in Figure 1.1. Figure 1.
C O E 3 0 5 L A B M A N U A L Figure 1.2: Layout of the FLIGHT-86 Training Board Loading FLIGHT86 host program, please wait... FLIGHT86 Controller Board, Host Program Version 2.1 Press ? and Enter for help - waiting for controller board response... ROM found at F000:C000 to F000:FFFF Flight Monitor ROM version 2.0 RAM found at 0000:0000 to 0000:FFFF - Figure 1.
C O E 3 0 5 L A B M A N U A L Table 1.
C O E 3 0 5 L A B M A N U A L 3. Now enter the assembly code one instruction at a time hitting ENTER after each instruction 4. Each time, the FLIGHT-86 responds by echoing the next address 5.
C O E 3 0 5 L A B M A N U A L Displaying/Modifying Memory Locations (Command M) To test the result of the above program enter M W 0050:0104 and press the Enter key. This will display the memory word at address 0050:0104 where the result of the above program is stored. Exit from this command by pressing the ESC key. Lets now change the content of the memory words stored at addresses 0050:0100 and 0050:0102. At the command prompt ‘-’, enter M W 0050:0100 and press the Enter key.
C O E 3 0 5 L A B M A N U A L The previous steps are shown below: -B S 0050:010D -G 0050:0100 Monitor Breakpoint at 0050:010D -R AX AX 000C 0001 BX 0000 -G 0050:010D User Break at 0050:0111 -M W 0050:0104 0050:0104 0001 0050:0106 00A1 - Single-Step Execution (Command S) This command is provided to allow the user to step through code one instruction at a time for debugging purposes. The display will be the next instruction address and opcode byte with, optionally, registers content.
C O E 3 0 5 L A B M A N U A L COMSEG SEGMENT BYTE PUBLIC 'CODE' ASSUME CS:COMSEG, DS:COMSEG, ES:COMSEG, SS:COMSEG ORG 0100h start: MOV AX, CS MOV DS, AX ; Set the data segment L1: MOV BX, 0 CMP JZ BX, L2 8 DL, L2 BX L1 5 4 2 7 6 3 5 1 8 A[BX] ; if the number is found in the list ; then end the search ; else increment BX CMP JZ INC JMP L2: INT A DB DB DB DB DB DB DB DB COMSEG ENDS END start ; ; ; ; Set BX to index of the 1st element in the list if BX exceeds the indices of the list then end th
C O E 3 0 5 L A B M A N U A L Exercises 1.1. Modify the program in Example 1.1 to perform the four basic operations: addition, subtraction, multiplication, and division. The required operation is specified by loading DX with the appropriate value (i.e. 1 for addition, 2 for subtraction, 3 for multiplication, and 4 for division). 1.2. Write a program to find the smallest number from a given list of numbers. Load this program into the FLIGTH-86 and test it.
C O E 3 0 5 L A B 2 Experiment M A N U A L Conducting Simple I/O Operations Using Flight 86 Training Kit Objective The aim of this lab experiment is to conduct simple I/O operations, reading state of switches and turning on/off LEDs provided on the Application Board, by programming 8255 PPI chip. Equipment FLIGHT-86 training board, Application Board, PC with Flight86 software, download cable Tasks to be Performed Interfacing the Application Board to the FLIGHT-86 training board.
C O E 3 0 5 L A B M A N U A L 2.1 Background The FLIGHT-86 training board ‘talks’ to the Application Board by means of an Input/Output (I/O) device (i.e. 8255 PPI). This device is quite intelligent, and can perform input, output, and handshaking. However, before it will carry out any of these tasks, it must be told what is required of it. For I/O, it consists of three 8-bit ports. These ports can be set up as input or output ports. Telling the PPI device how to perform is known as INITIALISATION.
C O E 3 0 5 L A B M A N U A L Figure 2.1: Layout of the Application Board Table 2.
C O E 3 0 5 L A B M A N U A L 2.3 Programming the 8255 PPI Chip The 8255 is a general-purpose parallel I/O interfacing device. It provides 24 I/O lines organized as three 8-bit I/O ports labeled A, B, and C. In addition to these three ports, a third port (Control) is used to program the chip. Each of the ports, A or B, can be programmed as an 8-bit input or output port. Port C can be divided in half, with the topmost or bottommost four bits programmed as inputs or outputs.
C O E 3 0 5 L A B M A N U A L Table 2.
C O E 3 0 5 L A B M A N U A L Lines 4 and 5 in the above code initialize the 8255 PPI chip in Mode 0, such that ports A and C are set as input ports while port B is set as an output port. Then, the program enters a continuous loop that reads the states of the switches into AL and displays them on the LEDs. Reading the states of the switches (line 7) is done through port A (00h), while displaying the output on the LEDs (line 8) is done through port B (02h). Example 2.
C O E 3 0 5 L A B M A N U A L Exercises 2.1. Write a program to generate the following based on the state of a particular switch Switch 1 : ON OFF Switch 2 : ON OFF 2.2. Generate a mod 8 counter and display it on LEDs Switch off all LEDs Generate a mod 256 counter and display it on LEDs Switch off all LEDs Switch 3 : ON Light LEDs one after another one at a time in a sequence from left to right (from first LED to Last LED). When one LED is on, all other LEDs must be switched off. ( i.e.
C O E 3 0 5 L A B 3 Experiment M A N U A L Generating Timing Sequences Objective The aim of this lab experiment is to generate timing sequences using software delays and programming 8253 Programmable Interval Timer (PIT) chip. Equipment Flight 8086 training board, the Application Board, PC with Flight86 software, download cable Tasks to be Performed Generate time delays using software delays and 8253 PIT chip.
C O E 3 0 5 L A B M A N U A L 3.1 Background It is often necessary to control how long certain actions last. This can be achieved using software delays, or more accurately by the use of a timer (i.e. 8253 PIT chip). In this experiment, you will learn how to generate time delays using both software delays and 8253 PIT chip. Also, you will learn how to use time delays to control the operation of some devices (e.g. LEDs and Relays), and to generate periodical waveforms of different frequencies. 3.
C O E 3 0 5 L A B M A N U A L Example 3.2: Write a program to turn ON an LED for 3 seconds, then turn it OFF for another 3 seconds, and repeat this cycle. COMSEG SEGMENT BYTE PUBLIC 'CODE' ASSUME CS:COMSEG, DS:COMSEG, ES:COMSEG, SS:COMSEG ORG 0100h Start: MOV AL, 99h ; initialize 8255 ports: OUT 06h, AL ; A and C in, B out MOV AL, 01h ; set bit 0 in AL to 1 ON_OFF: OUT 02h, AL ; turn on/off LED 0 MOV DL, 25 ; delay of 25*0.
C O E 3 0 5 L A B M A N U A L Figure 3.1: The 8253 PIT circuit diagram Each one of the previous registers has a unique address, and can be accessed using I/O operations (i.e. IN and OUT). Table 3.1, shows the addresses assigned to four registers in the FLIGHT-86 board. Table 3.
C O E 3 0 5 L A B M A N U A L 3. Read/Load Most Significant Byte (MSB): only the high byte of the counter can be read or loaded 4. Read/Load Least LSB then MSB: allows two bytes to be read from or loaded into the counter such that the LSB comes first. Figure 3.2: Control Word Format of the 8253 PIT Chip As indicated in Figure 3.2, there are six counting modes: Mode 0 - Interrupt on Terminal Count: The output goes low after the mode set operation, and remains low while counting down.
C O E 3 0 5 L A B M A N U A L Figure 3.
C O E 3 0 5 L A B M A N U A L In order to program any one of the three counters in a certain mode, you need to do two things. First, send a control word to the Control Word Register. Then, load a proper value into the counter register. These two steps are illustrated in the following example. Example 3.3: Write an assembly code to do the following: (1) Set Counter0 as a 16-bit binary counter operating in Mode0 (2) Load Counter0 with the proper value, such that OUT0 goes high after 0.025 seconds.
C O E 3 0 5 L A B M A N U A L interrupt pointer to enable the correct Interrupt Service Routine (ISR) to be executed. The 8259 PIC chip can be programmed to perform a number of modes of operation, which may be changed dynamically at any time in the program. Programming the 8253 PIC chip is not covered in this experiment. Instead, you will be given the necessary code to set the chip in a proper mode of operation. When the output of Counter0/Counter1 goes high, it generates a request on IR6/IR7.
C O E 3 0 5 L A B M A N U A L 18 19 20 21 22 23 24 25 26 ; initialize the 8259 PIC chip MOV AL, 17h OUT 10h, AL MOV AL, 20h OUT 12h, AL MOV AL, 03h OUT 12h, AL MOV AL, 3Fh OUT 12h, AL 27 28 29 30 ; initialize 8253 PIT chip (00110110 = 36h) ; Counter0, load MSB then LSB, mode 3, binary MOV AL, 36h OUT 0Eh, AL 31 32 33 34 35 ; counter loaded with F000h for 25 ms delay MOV AL, 00h OUT 08h, AL ; first load low byte MOV AL, 0F0h OUT 08h, AL ; now load high byte 36 37 STI MOV DL, 120 38 ; start of mai
C O E 3 0 5 L A B M A N U A L In the previous program, lines 6 and 7 set the ES segment to 0000h, which is the base address of the IVT. Lines 9 and 12 load the starting address of the ISR (IR6_ROUTINE) into the IVT. This routine will handle any request on IR6. Lines 16 and 17 initialize the 8255 PPI chip. Lines 19 to 26 initialize the 8259 PIC chip. Lines 29 and 20 initialize the 8253 PIT chip. Lines 32 to 35 load the Counter0 with the value F000h.
C O E 3 0 5 L A B 4 Experiment M A N U A L Analog to Digital & Digital to Analog Conversion Objective The aim of this lab experiment is to study the Analog to Digital conversion and Digital to Analog conversion. Equipment Flight 8086 training board, Application board, PC with Flight86 software, download cable. Tasks to be Performed Simulation of a A/D conversion employing successive approximation method using D/A converter Use a D/A converter to perform the following: 1.
C O E 3 0 5 L A B M A N U A L 4.1 Background In any computer controlled process it may be required to monitor analog values, i.e. the output of a voltmeter or strain gauge. In order to do this, the analog signal must be first converted into a digital value using an Analog-to-Digital Converter (A/D). On the other hand, Digital-to-Analog Converters (D/A) can be used to convert a digital output from the computer into an analog value.
C O E 3 0 5 L A B M A N U A L Example 4.1: Write a program to simulate a simple A/D converter. Use the variable voltage source (UR6) as your analog source. The program should display one HEX digit (0-F) representing the digital value of the voltage input.
C O E 3 0 5 L A B M A N U A L The previous code uses two functions, namely display_voltage and putc, to display the digital value corresponding to the input voltage. The first function converts the digital (binary) value of the input voltage into an ASCII character, and calls putc to display it on the screen. The two functions are given in two separate files display_voltage.asm and putc.asm, so that you can include these two files in your code using the INCLUDE directive. 4.
C O E 3 0 5 7 8 L A B M A N U A L MOV AL, 0 ; turn off all LEDs OUT 02h, AL 9 10 L1: MOV SI, OFFSET Table ; 1st element in the table MOV BL, 36 ; number of elements in the table 11 12 L2: LODSB ; load AL from the table OUT 02h, AL; and output the value to D/A 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 DEC BL JZ L2 JMP L1 ; ; ; ; count down table loop if not zero if zero then return to the start of the table DB
C O E 3 0 5 L A B M A N U A L This program reads the digital values form Table and output them to Port-A, then the D/A converter converts them to the corresponding analog voltages. Notice that the values in Table can generate only one cycle of the SIN wave. Therefore, the digital values in Table are output continuously to the D/A converter to generate a continuous SIN wave. Table 4.1: SIN Table Degree SIN(Degree) Assigned Voltage Corresponding Digital Value 0 0.000 1.27 127 10 0.174 1.
C O E 3 0 5 L A B M A N U A L Exercises 6.1. Consider Example 4.1. Describe how you would minimize the number of digital values required to find the unknown voltage. 6.2. How could you vary the frequency of the SIN wave generated in Example4.2? 6.3. Use the D/A converter to perform the following: a. Staircase waveform generation b. Saw-tooth waveform generation 6.4. The bar-graph (U10) is essentially a bank of 10 LEDs.
C O E 3 0 5 L A B 5 Experiment M A N U A L Controlling DC Motors Objective The aim of this lab experiment is to control a small DC motor.
C O E 3 0 5 L A B M A N U A L 5.1 DC Motor The Application Board contains a small DC motor that can be operated in the forward or reverse direction. The operation of this DC motor is controlled by bits 6 and 7 on Port-A as shown in Table 5.1. Table 5.1: Operation Modes of the DC Motor Bit6 0 0 1 1 Bit7 0 1 0 1 Operation Stop Reverse Direction Forward Direction Stop The following example shows you how to run the DC motor in the forward and reverse direction for a specific time. Example 4.
C O E 3 0 5 L A B M A N U A L 5.3 Controlling the Speed of the DC Motor When the DC motor is ON (forward/reverse), it operates in its maximum speed. However, the speed of the motor can be controlled using pulse width modulation (PWM). PWM is a common technique for speed control. A good analogy is bicycle riding. You peddle (exert energy) and then coast (relax) using your momentum to carry you forward.
C O E 3 0 5 L A B M A N U A L 16 17 18 19 ; initialize the 8255 PPI chip: ; A and C input ports, B output port MOV AL, 99h OUT 06h, AL 20 21 22 23 24 25 26 27 28 ; initialize the 8259 PIC chip MOV AL, 17h OUT 10h, AL MOV AL, 20h OUT 12h, AL MOV AL, 03h OUT 12h, AL MOV AL, 3Fh OUT 12h, AL 29 30 31 32 33 34 35 36 ; initialize 8253 PIT chip (00110000 = 30h) ; Counter0, load MSB then LSB, mode 0, binary MOV AL, 30h OUT 0Eh, AL ; initialize 8253 PIT chip (01110000 = 70h) ; Counter1, load MSB then LSB, mo
C O E 3 0 5 70 71 72 73 L A B M A N U A L OUT 0Ah, AL MOV AL, 0FFh OUT 0Ah, AL IRET ; first load low byte ; now load high byte 74 75 ; Interrupt Service Routine (ISR) for IR7 ; this routine turn on the motor and reload Counter 0 76 78 79 80 IR7_ROUTINE: MOV AL, 40h OUT 02h, AL ; turn on the motor 81 82 83 84 85 ; counter0 loaded with FFFFh MOV AL, 0FFh OUT 08h, AL ; first load low byte MOV AL, 0FFh OUT 08h, AL ; now load high byte 86 IRET 87 88 COMSEG END ENDS start Exercises 5.1.
C O E 3 0 5 L A B 6 Experiment M A N U A L Interfacing a Hyper Terminal to the Flight 86 Kit Objective The aim of this lab experiment is to interface a Hyper Terminal to 8086 processor by programming the 8251 USART.
C O E 3 0 5 L A B M A N U A L 6.1 Background The Intel 8251 Universal Synchronous/Asynchronous Receiver/Transmitter (USART), designed for data communication with Intel's microprocessor families. It is used as a peripheral device and is programmed by the CPU to operate using many serial data transmission techniques. The USART accepts data characters from the CPU in parallel format and then converts them into a continuous serial data stream.
C O E 3 0 5 L A B M A N U A L Table 6.1: The 8251 Registers Register Data Mode Control Status Activity Allowed Read/Write Write Only Write Only Read Only Actual Port Address 18h 1Ah 1Ah 1Ah Control Words The 8251 USART chip can be programmed using two types of control words: (1) The Mode Instruction, which must follow a reset (internal or external) to specify the general operation of the chip. This control word can be sent through the MODE register according to the format shown in Figure 6.1 (a).
C O E 3 0 5 L A B M A N U A L Figure 6.1: 8251 Control Words Table 6.1: 8251 Status Word 0 1 2 BIT Transmitter Ready Receiver Buffer Full Transmitter Buffer Empty 3 Parity Error 4 Overrun Error 5 Framing Error 6 Synchronous Detect/ Break Detect Data Set Ready 7 Description This bit is set when the transmitter is ready to receive a new character for transmission from the CPU. This bit s set when a character is received on the serial input.
C O E 3 0 5 L A B M A N U A L 6.2 Programming the 8251 USART Chip In order to program the 8251 USART chip in asynchronous mode, you need to do the following: 1. Set the receiver/transmitter input clock to the desired baud rate. In the FLIGHT-86, this is done by programming Counter 2 of the 8253 PIT chip. 2. Send asynchronous mode instruction with the desired format. 3. Send a command instruction to enable the transmitter/receiver.
C O E 3 0 5 L A B M A N U A L Example 4.1: Write a program that continuously reads one character from the keyboard and displays it on the Hyper Terminal.
C O E 3 0 5 L A B M A N U A L Note that once you run the program of Example 6.1 on the FLIGHT-86, you need to close the F86GO program to allow the Hyper Terminal to communicate with the program through the serial cable. This is because the serial communication port may not be used by more than one application at the same time. Exercises 6.1. Write a program to read a string from the keyboard and display it on the Hyper Terminal in a reverse order. 6.2.
C O E 3 0 5 L A B 3 Part M A N U A L Mini Project I In this part, students will be carrying out a mini project of designing an interface board for certain application. This mini project will be carried out in groups. The students will use PCB design tools for entering schematic and generating layout for fabrication of the interface card. The interface board will need to be interfaced to their fabricated processor board.
C O E 3 0 5 L A B M A N U A L Appendices 8086 Microprocessor 8284 Clock Generator TTL Data Sheets 8255 Programmable Peripheral Interface (PPI) 8253 Programmable Interval Timer (PIT) 8259 Programmable Interrupt Controller (PIC) 8251 Universal Synchronous Asynchronous Receiver Transmitter (USART) 67
8086 16-BIT HMOS MICROPROCESSOR 8086/8086-2/8086-1 Y Direct Addressing Capability 1 MByte of Memory Y Architecture Designed for Powerful Assembly Language and Efficient High Level Languages Y 14 Word, by 16-Bit Register Set with Symmetrical Operations Y 24 Operand Addressing Modes Y Bit, Byte, Word, and Block Operations Y 8 and 16-Bit Signed and Unsigned Arithmetic in Binary or Decimal Including Multiply and Divide Y Range of Clock Rates: 5 MHz for 8086, 8 MHz for 8086-2, 10 MHz for 8086-1 Y
8086 Table 1. Pin Description The following pin function descriptions are for 8086 systems in either minimum or maximum mode. The ‘‘Local Bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional bus buffers). Symbol Pin No. Type Name and Function AD15 –AD0 2–16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1), and data (T2, T3, TW, T4) bus.
8086 Table 1. Pin Description (Continued) Symbol Pin No. Type Name and Function READY 22 I READY: is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The READY signal from memory/IO is synchronized by the 8284A Clock Generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met.
8086 Table 1. Pin Description (Continued) Symbol Pin No. Type Name and Function S2, S1, S0 (Continued) 26–28 O These signals float to 3-state OFF in ‘‘hold acknowledge’’. These status lines are encoded as shown.
8086 Table 1. Pin Description (Continued) Symbol Pin No. Type Name and Function QS1, QS0 24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue operation is performed. QS1 and QS0 provide status to allow external tracking of the internal 8086 instruction queue.
8086 bytes, addressed as 00000(H) to FFFFF(H). The memory is logically divided into code, data, extra data, and stack segments of up to 64K bytes each, with each segment falling on 16-byte boundaries. (See Figure 3a.) FUNCTIONAL DESCRIPTION General Operation The internal functions of the 8086 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the block diagram of Figure 1.
8086 address FFFF0H through FFFFFH are reserved for operations including a jump to the initial program loading routine. Following RESET, the CPU will always begin execution at location FFFF0H where the jump must be. Locations 00000H through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt types has its service routine pointed to by a 4-byte pointer element consisting of a 16-bit segment address and a 16-bit offset address.
8086 231455 – 5 Figure 4a. Minimum Mode 8086 Typical Configuration 231455 – 6 Figure 4b.
8086 can occur between 8086 bus cycles. These are referred to as ‘‘Idle’’ states (Ti) or inactive CLK cycles. The processor uses these cycles for internal housekeeping. During T1 of any bus cycle the ALE (Address Latch Enable) signal is emitted (by either the processor or the 8288 bus controller, depending on the MN/MX strap). At the trailing edge of this pulse, a valid address and certain status information for the cycle may be latched.
86 Status bits S3 through S7 are multiplexed with highorder address bits and the BHE signal, and are therefore valid during T2 through T4. S3 and S4 indicate which segment register (see Instruction Set description) was used for this bus cycle in forming the address, according to the following table: S4 S3 Characteristics 0 (LOW) 0 Alternate Data (extra segment) 0 1 Stack 1 (HIGH) 0 Code or None 1 1 Data NMI asserted prior to the 2nd clock after the end of RESET will not be honored.
8086 MASKABLE INTERRUPT (INTR) HALT The 8086 provides a single interrupt request input (INTR) which can be masked internally by software with the resetting of the interrupt enable FLAG status bit. The interrupt request signal is level triggered. It is internally synchronized during each clock cycle on the high-going edge of CLK. To be responded to, INTR must be present (HIGH) during the clock period preceding the end of the current instruction or the end of a whole move for a blocktype instruction.
8086 EXTERNAL SYNCHRONIZATION VIA TEST SYSTEM TIMINGÐMINIMUM SYSTEM As an alternative to the interrupts and general I/O capabilities, the 8086 provides a single softwaretestable input known as the TEST signal. At any time the program may execute a WAIT instruction. If at that time the TEST signal is inactive (HIGH), program execution becomes suspended while the processor waits for TEST to become active. It must remain active for at least 5 CLK cycles.
8086 lines D7 –D0 as supplied by the inerrupt system logic (i.e., 8259A Priority Interrupt Controller). This byte identifies the source (type) of the interrupt. It is multiplied by four and used as a pointer into an interrupt vector lookup table, as described earlier.
8086 ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifications are subject to change without notice. Ambient Temperature Under Bias ÀÀÀÀÀÀ0§ C to 70§ C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C Voltage on Any Pin with Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 1.0V to a 7V Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2.5W D.C. CHARACTERISTICS Symbol *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage.
8086 A.C.
8086 A.C.
8086 A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 231455-11 A.C. Testing: Inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at 1.5V for both a Logic ‘‘1’’ and ‘‘0’’.
8086 WAVEFORMS (Continued) MINIMUM MODE (Continued) 231455 – 14 SOFTWARE HALTÐ RD, WR, INTA e VOH DT/R e INDETERMINATE NOTES: 1. All signals switch between VOH and VOL unless otherwise specified. 2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted. 3. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control signals shown for second INTA cycle. 4. Signals at 8284A are shown for reference only. 5.
8086 A.C. CHARACTERISTICS MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS Symbol 8086 Parameter 8086-1 8086-2 Min Max Min Max Min Max 500 100 500 125 500 Units TCLCL CLK Cycle Period 200 TCLCH CLK Low Time 118 53 68 ns TCHCL CLK High Time 69 39 44 ns Test Conditions ns TCH1CH2 CLK Rise Time 10 10 10 ns From 1.0V to 3.5V TCL2CL1 CLK Fall Time 10 10 10 ns From 3.5V to 1.
8086 A.C.
8086 A.C.
8086 WAVEFORMS MAXIMUM MODE 231455 – 15 22
8086 WAVEFORMS (Continued) MAXIMUM MODE (Continued) 231455 – 16 NOTES: 1. All signals switch between VOH and VOL unless otherwise specified. 2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted. 3. Cascade address is valid between first and second INTA cycle. 4. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control for pointer address is shown for second INTA cycle. 5.
8086 WAVEFORMS (Continued) ASYNCHRONOUS SIGNAL RECOGNITION 231455 – 17 NOTE: 1. Setup requirements for asynchronous signals only to guarantee recognition at next CLK. BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY) RESET TIMING 231455 – 18 231455 – 19 REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY) 231455 – 20 NOTE: The coprocessor may not drive the buses outside the region shown without risking contention.
8086 WAVEFORMS (Continued) HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY) 231455 – 21 25
8086 Table 2.
8086 Table 2. Instruction Set Summary (Continued) Mnemonic and Description ARITHMETIC Instruction Code 76543210 76543210 76543210 76543210 data if s: w e 01 ADD e Add: Reg./Memory with Register to Either 000000dw mod reg r/m Immediate to Register/Memory 100000sw mod 0 0 0 r/m data Immediate to Accumulator 0000010w data data if w e 1 ADC e Add with Carry: Reg.
8086 Table 2.
8086 Table 2.
8086 Table 2.
82C84A CMOS Clock Generator Driver March 1997 Features Description • Generates the System Clock For CMOS or NMOS Microprocessors The Intersil 82C84A is a high performance CMOS Clock Generatordriver which is designed to service the requirements of both CMOS and NMOS microprocessors such as the 80C86, 80C88, 8086 and the 8088. The chip contains a crystal controlled oscillator, a divide-bythree counter and complete “Ready” synchronization and reset logic.
82C84A Functional Diagram 11 D RES X1 X2 F/C EF1 CSYNC RDY1 AEN1 RDY2 AEN2 ASYNC 16 Q 10 RESET CK 17 XTAL OSCILLATOR 12 OSC 13 ÷3 SYNC ÷2 SYNC 2 PCLK 14 1 4 8 CLK 3 6 CK D Q FF1 7 CK 5 D Q FF2 15 CONTROL PIN LOGICAL 1 LOGICAL 0 F/C External Clock Crystal Drive RES Normal Reset RDY1, RDY2 Bus Ready Bus Not Ready AEN1, AEN2 Address Disabled Address Enable ASYNC 1 Stage Ready Synchronization 2 Stage Ready Synchronization 4-288 READY
82C84A Pin Description SYMBOL NUMBER TYPE DESCRIPTION AEN1, AEN2 3, 7 I ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are useful in system configurations which permit the processor to access two MultiMaster System Busses. In non-Multi-Master configurations, the AEN signal inputs are tied true (LOW). RDY1, RDY2 4, 6 I BUS READY (Transfer Complete).
82C84A Functional Description Clock Outputs Oscillator The oscillator circuit of the 82C84A is designed primarily for use with an external parallel resonant, fundamental mode crystal from which the basic operating frequency is derived. The crystal frequency should be selected at three times the required CPU clock. X1 and X2 are the two crystal input crystal connections.
82C84A Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance . . . . . . . . . . . . . . . . θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 80 20 CLCC Package . . . . . . . . . . . . . . . . . . 95 28 PDIP Package . .
82C84A AC Electrical Specifications VCC = +5V± 10%, TA = 0oC to +70oC (C82C84A), TA = -40oC to +85oC (I82C84A), TA = -55oC to +125oC (M82C84A) LIMITS SYMBOL PARAMETER MIN MAX UNITS (NOTE 1) TEST CONDITIONS TIMING REQUIREMENTS (1) TEHEL External Frequency HIGH Time 13 - ns 90%-90% VIN (2) TELEH External Frequency LOW Time 13 - ns 10%-10% VIN (3) TELEL EFI Period 36 - ns XTAL Frequency 2.
82C84A Timing Waveforms NAME EFI I OSC O CLK (3) I/O tOLCH (29) O (19) tCLCH (17) tCLCL tCL2CL1 (21) tCH1CH2 (20) PCLK CSYNC O (30) tOLCL tPLPH (23) tYHEH (12) (16) tCLI1H (22) tPHPL (15) tI1HCL (14) tYHYL RES I RESET O (26) tCLIL NOTE: All timing measurements are made at 1.5V, unless otherwise noted. FIGURE 2.
82C84A Test Load Circuits 2.25V R = 740Ω FOR ALL OUTPUTS EXCEPT CLK 463Ω FOR CLK OUTPUT OUTPUT FROM DEVICE UNDER TEST CL (SEE NOTE 3) NOTES: 1. CL =100pF for CLK output. 2. CL = 50pF for all outputs except CLK. 3. CL = Includes probe and jig capacitance. FIGURE 5. TEST LOAD MEASUREMENT CONDITIONS PULSE GENERATOR LOAD (SEE NOTE 1) CLK X1 C1 CLK EF1 LOAD (SEE NOTE 1) VCC X2 C2 F/C F/C CSYNC CSYNC FIGURE 6.
82C84A Burn-In Circuits MD82C84A CERDIP VCC C1 R1 F9 VCC GND R2 R2 1 18 2 17 3 16 R1 R2 F6 OPEN R3 R1 F5 VCC GND F7 4 R2 15 F10 R1 5 R2 14 F1 R1 R1 6 13 7 12 R2 R1 F8 VCC GND F0 R1 R2 R2 R1 R2 8 11 9 10 R2 R2 F11 VCC GND F12 VCC GND MR82C84A CLCC F0 R4 F9 20 19 18 5 17 6 16 7 15 14 8 NOTES: VCC = 5.5V ±0.5V, GND = 0V. VIH = 4.5V ±10%. VIL = -0.2 to 0.4V. R1 = 47kΩ, ±5%. R2 = 10kΩ, ±5%. R3 = 2.2kΩ, ±5%. R4 = 1.2kΩ, ±5%. C1 = 0.01µF (minimum). F0 = 100kHz ±10%.
82C84A Die Characteristics DIE DIMENSIONS: 66.1 x 70.5 x 19 ± 1mils GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ METALLIZATION: Type: Si - AI Thickness: 11kÅ ± 1kÅ WORST CASE CURRENT DENSITY: 1.42 x 105 A/cm2 Metallization Mask Layout 82C84A AEN1 PCLK CSYNC VCC X1 X2 RDY1 ASYNC READY RDY2 EFI AEN2 F/C CLK GND RESET RES OSC All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
DM74LS373/DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components.
Connection Diagrams (Continued) ’LS374 DS006431-2 Order Number DM54LS374J, DM54LS374W, DM74LS374WM or DM74LS374N See Package Number J20A, M20B, N20A or W20A Function Tables DM54/74LS373 Output Enable Control G D Output L L H H H H L L L L X Q0 H X X Z H = High Level (Steady State), L = Low Level (Steady State), X = Don’t Care ↑ = Transition from low-to-high level, Z = High Impedance State Q0 = The level of the output before steady-state input conditions were established.
Logic Diagrams DM54/74LS334 Transparent Latches DM54/74LS374 Positive-Edge-Triggered Flip-Flops DS006431-3 DS006431-4 3 www.fairchildsemi.
Absolute Maximum Ratings (Note 1) Supply Voltage Input Voltage Storage Temperature Range Operating Free Air Temperature Range DM54LS DM74LS 7V 7V −65˚C to +150˚C −55˚C to +125˚C 0˚C to +70˚C Recommended Operating Conditions Symbol Parameter DM54LS373 DM74LS373 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Votage VIL Low Level Input Voltage 0.7 0.8 V IOH High Level Output Current −1 −2.
’LS373 Electrical Characteristics (Continued) over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 40 mA (Note 4) ICC VCC = Max, OC = 4.
Recommended Operating Conditions Symbol (Continued) Parameter DM54LS374 Min tW Nom DM74LS374 Max Min Pulse Width Clock High 15 15 (Note 8) Clock Low 15 15 Units Max ns tSU Data Setup Time (Notes 7, 8) 20↑ 20↑ tH Data Hold Time (Notes 7, 8) 1↑ 1↑ TA Free Air Operating Temperature −55 125 Nom ns ns 0 70 ˚C Note 7: The symbol (↑) indicates the rising edge of the clock pulse is used for reference. Note 8: TA = 25˚C and VCC = 5V.
’LS374 Switching Characteristics at VCC = 5V and TA = 25˚C RL = 667Ω Symbol CL = 45 pF Parameter Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time Max 35 CL = 150 pF Min Units Max 20 MHz 28 32 ns 28 38 ns 28 44 ns 28 44 ns Low to High Level Output tPHL Propagation Delay Time High to Low Level Output tPZH Output Enable Time to High Level Output tPZL Output Enable Time to Low Level Output tPHZ Output Disable Time 20 ns 25 ns from High Level Output (Note 11) tPL
DM74LS245 3-STATE Octal Bus Transceiver General Description These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input. The enable input (G)can be used to disable the device so that the buses are effectively isolated.
Absolute Maximum Ratings (Note 1) Supply Voltage Input Voltage DIR or G A or B Operating Free Air Temperature Range DM54LS and 54LS DM74LS Storage Temperature Range 7V 7V 5.5V −55˚C to +125˚C 0˚C to +70˚C −65˚C to +150˚C Recommended Operating Conditions Symbol Parameter DM54LS245 DM74LS245 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage 0.7 0.
Switching Characteristics VCC = 5V, TA = 25˚C DM54/74 Symbol Parameter Conditions LS245 Min tPLH Propagation Delay Time, Low-to-High-Level Output tPHL Propagation Delay Time, High-to-Low-Level Output tPZL Output Enable Time to Low Level tPZH Output Enable Time to High Level tPLZ Output Disable Time from Low Level tPHZ Output Disable Time from High Level tPLH Propagation Delay Time, Low-to-High-Level Output tPHL Propagation Delay Time, High-to-Low-Level Output tPZL Output Enable Time to
E2O0020-27-X3 This version: Jan. 1998 MSM82C55A-2RS/GS/VJS Previous version: Aug. 1996 ¡ Semiconductor MSM82C55A-2RS/GS/VJS ¡ Semiconductor CMOS PROGRAMMABLE PERIPHERAL INTERFACE This product is not available in Asia and Oceania. GENERAL DESCRIPTION The MSM82C55A-2 is a programmable universal I/O interface device which operates as high speed and on low power consumption due to 3m silicon gate CMOS technology.
¡ Semiconductor MSM82C55A-2RS/GS/VJS CIRCUIT CONFIGURATION 8 VCC 8 GND Group A Port A (8) 8 PA0 - PA7 8 Group A Control 8 D 0 - D7 Data Bus Buffer Internal Bus Line 4 8 4 8 RD WR RESET CS Read/ Write Control Logic Group A Port C (High Order 4 Bits) Group B Port C (Low Order 4 Bits) 4 PC4 - PC7 4 PC0 - PC3 Group B Control 8 Group B Port B (8) 8 PB0 - PB7 A0 A1 2/26
¡ Semiconductor MSM82C55A-2RS/GS/VJS PIN CONFIGURATION (TOP VIEW) 40 pin Plastic DIP 1 2 3 4 RD 5 CS 6 GND 7 A1 8 A0 9 PC7 10 PC6 11 PC5 12 PC4 13 PC0 14 PC1 15 PC2 16 PC3 17 PB0 18 PB1 19 PB2 20 PA3 PA2 PA1 PA0 34 WR 24 23 22 21 PB6 PB5 PB4 PB3 D4 D5 D6 D7 VCC PB7 D0 D1 D2. D3 D4 D5 D6 D7 VCC PB7 40 WR 41 PA7 43 PA5 42 PA6 1 NC 44 PA4 2 PA3 6 RD 5 PA0 39 38 37 36 35 34 33 32 31 30 29 RESET D0 D1 D2.
¡ Semiconductor MSM82C55A-2RS/GS/VJS ABSOLUTE MAXIMUM RATINGS Parameter Rating Conditions Symbol Unit MSM82C55A-2RS MSM82C55A-2GS MSM82C55A-2vJS VCC Supply Voltage Input Voltage Ta = 25°C with respect to GND VIN Output Voltage VOUT TSTG Storage Temperature Power Dissipation V –0.5 to VCC +0.5 V –0.5 to VCC +0.5 V –55 to +150 — PD –0.5 to +7 Ta = 25°C 1.0 °C 0.7 1.
¡ Semiconductor AC CHARACTERISTICS Parameter MSM82C55A-2RS/GS/VJS (VCC = 4.5 V to 5.5 V, Ta = –40 to +85°C) MSM82C55A-2 Symbol Unit Remarks Min. Max.
¡ Semiconductor MSM82C55A-2RS/GS/VJS TIMING DIAGRAM Basic Input Operation (Mode 0) tRR RD tIR tHR Port Input tAR tRA CS, A1, A0 D7 - D0 tRD tDF Basic Output Operation (Mode 0) tWW WR tDW tWD D 7 - D0 tAW tWA CS, A1, A0 Port Output tWB Strobe Input Operation (Mode 1) tST STB tSIB IBF tSIT tRIB INTR tRIT RD tPH Port Input tPS 6/26
¡ Semiconductor MSM82C55A-2RS/GS/VJS Strobe Output Operation (Mode 1) WR tAOB OBF tWOB INTR tWIT ACK tAIT tAK Port Output tWB Bidirectional Bus Operation (Mode 2) WR tAOB OBF tWOB INTR tAK ACK STB tST tSIB IBF tAD tPS tKD Port A RD tPH tRIB 7/26
¡ Semiconductor MSM82C55A-2RS/GS/VJS OUTPUT CHARACTERISTICS (REFERENCE VALUE) 1 Output "H" Voltage (VOH) vs. Output Current (IOH) Output "H" Voltage VOH (V) 5 Ta = –40 to + 85°C VCC = 5.0 V 4 3 2 1 0 0 –1 –2 –3 –4 –5 Output Current IOH (mA) Output "L" Voltage (VOL) vs. Output Current (IOL) 5 Output "L" Voltage VOL (V) 2 4 3 2 VCC = 5.
¡ Semiconductor MSM82C55A-2RS/GS/VJS PIN DESCRIPTION Pin No. D 7 - D0 Item Bidirectional Data Bus Input/Output Function Input and Output These are three-state 8-bit bidirectional buses used to write and read data upon receipt of the WR and RD signals from CPU and also used when control words and bit set/reset data are transferred from CPU to MSM82C55A-2. This signal is used to reset the control register and all internal registers when it is in high level.
¡ Semiconductor MSM82C55A-2RS/GS/VJS BASIC FUNCTIONAL DESCRIPTION Group A and Group B When setting a mode to a port having 24 bits, set it by dividing it into two groups of 12 bits each.
¡ Semiconductor MSM82C55A-2RS/GS/VJS OPERATIONAL DESCRIPTION Control Logic Operations by addresses and control signals, e.g., read and write, etc.
¡ Semiconductor MSM82C55A-2RS/GS/VJS Precaution for Mode Selection The output registers for ports A and C are cleared to f each time data is written in the command register and the mode is changed, but the port B state is undefined. Bit Set/Reset Function When port C is defined as output port, it is possible to set (set output to 1) or reset (set output to 0) any one of 8 bits without affecting other bits as shown below. D7 D6 D5 D4 D3 D2 D1 D0 Definition of set/reset for a desired bit.
¡ Semiconductor MSM82C55A-2RS/GS/VJS Control Word Group A Type D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Group B Port A High Order 4 Bits of Port C Port B Low Order 4 Bits of Port C 1 1 0 0 0 0 0 0 0 Output Output Output Output 2 1 0 0 0 0 0 0 1 Output Output Output Input 3 1 0 0 0 0 0 1 0 Output Output Input Output 4 1 0 0 0 0 0 1 1 Output Output Input Input 5 1 0 0 0 1 0 0 0 Output Input Output Output 6 1 0 0 0 1 0 0 1 Output Input
¡ Semiconductor MSM82C55A-2RS/GS/VJS OBF (Output buffer full flag output) This signal when turned to low level indicates that data is written to the specified port upon receipt of the WR signal from the CPU. This signal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK. ACK (Acknowledge input) This signal when turned to low level indicates that the terminal has received data.
¡ Semiconductor MSM82C55A-2RS/GS/VJS Port C Function Allocation in Mode 1 Combination of Input/Output Group A: Input Group B: Input Port C Group A: Input Group A: Output Group B: Output Group B: Input Group A: Output Group B: Output PC0 INTRB INTRB INTRB INTRB PC1 IBFB OBFB IBFB OBFB PC2 STBB ACKB STBB ACKB PC3 INTRA INTRA INTRA INTRA PC4 STBA STBA I/O I/O PC5 IBFA IBFA I/O I/O PC6 I/O I/O ACKA ACKA PC7 I/O I/O OBFA OBFA Note: I/O is a bit not used as the contr
¡ Semiconductor MSM82C55A-2RS/GS/VJS (b) When group A is mode 1 input and group B is mode 1 output. D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 1 0 ¥ Selection of I/O of PC6 and PC7 when not defined as a control pin. 1 = Input 0 = Output RD WR PA7 - PA0 PC4 PC5 PC3 PC6, PC7 PB7 - PB0 PC1 PC2 PC0 8 2 STBA IBFA INTRA I/O 8 Group A: Mode 1 Input Group B: Mode 1 Output OBFB ACKB INTRB 3.
¡ Semiconductor MSM82C55A-2RS/GS/VJS INTR (Interrupt request output) This signal is used to interrupt the CPU and its operation in the same as in mode 1. There are two INTE flip-flops internally available for input and output to select either interrupt of input or output operation. The INTE1 is used to control the interrupt request for output operation and it can be reset by the bit set for PC6.
¡ Semiconductor MSM82C55A-2RS/GS/VJS D7 D6 D5 D4 D3 D2 D1 D0 1 1 ¥ ¥ ¥ 1 1 ¥ As all of 8 bits of port C become control pins in this case, D3 and D0 bits are treated as "Don't Care". No I/O specification is required for mode 2, since it is a bidirectional operation. This bit is therefore treated as "Don't Care". When group A is set to mode 2, this bit is treated as "Don't Care".
¡ Semiconductor MSM82C55A-2RS/GS/VJS 4. When Group A is Different in Mode from Group B Group A and group B can be used by setting them in different modes each other at the same time. When either group is set to mode 1 or mode 2, it is possible to set the one not defined as a control pin in port C to both input and output as port which operates in mode 0 at the 3rd and 0th bits of the control word.
¡ Semiconductor MSM82C55A-2RS/GS/VJS 5. Port C Status Read When port C is used for the control signal, that is, in either mode 1 or mode 2, each control signal and bus status signal can be read out by reading the content of port C.
¡ Semiconductor MSM82C55A-2RS/GS/VJS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages.
¡ Semiconductor MSM82C55A-2RS/GS/VJS Differences between MSM82C55A-5 and MSM82C55A-2 1) Manufacturing Process These devices use a 3 m Si-Gate CMOS process technology. The MSM82C55A-2 is about 7% smaller in chip size than the MSM82C55A-5 as the MSM82C55A2 changed its output characteristics. 2) Function Item Internal latch during writing into the command register MSM82C55A-5 Only ports A and C are cleared. Port B is not cleared. MSM82C55A-2 All ports are cleared.
¡ Semiconductor Parameter MSM82C55A-2RS/GS/VJS Symbol MSM82C55A-5 MSM82C55A-2 Address Hold Time for WR Rising tWA 30 ns minimum 20 ns minimum WR Pulse Width tWW 300 ns minimum 150 ns minimum Data Setup Time for WR Rising tDW 1000 ns minimum 50 ns minimum Data Hold Time for WR Rising tWD 40 ns minimum 30 ns minimum Defined Data Output Time From WR Rising tWB 350 ns maximum 200 ns maximum Port Data Hold Time for RD Rising tHR 20 ns minimum 10 ns minimum ACK Pulse Width tAK 300 n
E2O0018-27-X2 This version: Jan. 1998 MSM82C53-2RS/GS/JS Previous version: Aug. 1996 ¡ Semiconductor MSM82C53-2RS/GS/JS ¡ Semiconductor CMOS PROGRAMMABLE INTERVAL TIMER This product is not available in Asia and Oceania. GENERAL DESCRIPTION The MSM82C53-2RS/GS/JS is programmable universal timers designed for use in microcomputer systems. Based on silicon gate CMOS technology, it requires a standby current of only 100 mA (max.) when the chip is in the nonselected state.
¡ Semiconductor MSM82C53-2RS/GS/JS FUNCTIONAL BLOCK DIAGRAM VCC GND 8 D7 - D0 Data Bus Buffer Counter CLK0 GATE0 #0 OUT0 Read/ Write Logic Counter CLK1 #1 OUT1 Control Word Register Counter CLK2 8 WR RD A0 GATE1 A1 CS GATE2 #2 OUT2 Internal Bus 2/19
¡ Semiconductor MSM82C53-2RS/GS/JS PIN CONFIGURATION (TOP VIEW) 24 pin Plastic DIP D7 1 24 Vcc D6 2 23 WR D5 3 22 RD D4 4 21 CS D3 5 20 A1 D2 6 19 A0 D1 7 18 CLK2 D0 8 17 OUT2 CLK0 9 16 GATE2 OUT0 10 15 CLK1 GATE0 11 14 GATE1 13 OUT1 GND 12 NC D7 D6 D5 32 pin Plastic SSOP NC D4 D3 D2 D1 D0 CLK0 NC OUT0 GATE0 GND NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC Vcc WR RD NC CS A1 A0 CLK2 OUT2 GATE2 NC CLK1 GATE1 OUT1 NC 26 RD 27 WR
¡ Semiconductor MSM82C53-2RS/GS/JS ABSOLUTE MAXIMUM RATINGS Parameter Rating Condition Symbol MSM82C53-2RS Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation VCC Respect to GND VIN VOUT TSTG MSM82C53-2JS –0.5 to + 7 V –0.5 to VCC + 0.5 V –0.5 to VCC + 0.5 V –55 to + 150 — PD Units MSM82C53-2GS 0.9 Ta = 25°C °C 0.7 0.9 W OPERATING RANGES Parameter Symbol Condition Range Unit Supply Voltage VCC VIL = 0.2 V, VIH = VCC -0.
¡ Semiconductor MSM82C53-2RS/GS/JS AC CHARACTERISTICS (VCC = 4.5 V to 5.
¡ Semiconductor MSM82C53-2RS/GS/JS TIMING CHART WriteTiming A0 - 1 CS tAW tWA D0 - 7 tDW WR tWD tWW Read Timing A0 - 7, CS tAR tRA tRR RD tRD tAD D0 - 7 tDF Valid High Impedance High Impedance Clock & Gate Timing tCLK tPWL CLK tPWH tGH tGS tGS GATE tGL tGH tGW tODG tOD OUT 6/19
¡ Semiconductor MSM82C53-2RS/GS/JS DESCRIPTION OF PIN FUNCTIONS Pin Symbol Name Input/Output Function D7 - D 0 Bidirectional Data Bus Input/Output Three-state 8-bit bidirectional data bus used when writing control words and count values, and reading count values upon reception of WR and RD signals from CPU. CS Chip Select Input Input RD Read Input Input Data can be transferred from MSM82C53-2 to CPU when this pin is at low level.
¡ Semiconductor MSM82C53-2RS/GS/JS DESCRIPTION OF BASIC OPERATIONS Data transfers between the internal registers and the external data bus is outlined in the following table.
¡ Semiconductor MSM82C53-2RS/GS/JS • Select Counter (SC0, SC1): Selection of set counter SC1 SC0 0 0 0 1 Counter #1 Selection 1 0 Counter #2 Selection 1 1 Illegal Combination Set Contents Counter #0 Selection • Read/Load (RL1, RL0): Count value Reading/Loading format setting Set Contents RL1 RL0 0 0 0 1 Reading/Loading of Least Significant Byte (LSB) 1 0 Reading/Loading of Most Significant Byte (MSB) 1 1 Reading/Loading of LSB Followed by MSB Counter Latch Operation • Mode (M2
¡ Semiconductor MSM82C53-2RS/GS/JS • Example of control word and count value setting Counter #0: Read/Load LSB only, Mode 3, Binary count, count value 3H Counter #1: Read/Load MSB only, Mode 5, Binary count, count value AA00H Counter #2: Read/Load LSB and MSB, Mode 0, BCD count, count value 1234 MVI A, 1EH OUT n3 Counter #0 control word setting MVI A, 6AH OUT n3 Counter #1 control word setting MVI A, B1H OUT n3 Counter #2 control word setting MVI A, 03H OUT n0 Counter #0 control value setting MVI
¡ Semiconductor MSM82C53-2RS/GS/JS Mode Definition • Mode 0 (terminal count) The counter output is set to “L” level by the mode setting. If the count value is then written in the counter with the gate input at “H” level (that is, upon completion of writing the MSB when there are two bytes), the clock input counting is started. When the terminal count is reached, the output is switched to “H” level and is maintained in this status until the control word and count value are set again.
¡ Semiconductor MSM82C53-2RS/GS/JS • Mode 4 (software trigger strobe) The counter output is switched to “H” level by the mode setting. Counting is started in the same way as described for mode 0. A single “L” pulse equivalent to one clock width is generated at the counter output when the terminal count is reached. This mode differs from 2 in that the “L” level output appears one clock earlier in mode 2, and that pulses are not repeated in mode 4.
¡ Semiconductor MSM82C53-2RS/GS/JS Mode 0 CLK WR (n = 4) OUT (GATE="H") (n = 2) 4 3 2 1 0 2 4 4 4 4 3 2 4 3 2 1 0 4 3 2 4 3 4 3 2 1 4 4 3 2 1 4 1 0 WR (n = 4) GATE OUT 1 0 2 1 0 2 1 2 1 2 4 3 2 1 Mode 1 CLK WR (n = 4) GATE OUT GATE OUT (n = 4) Mode 2 CLK WR (n = 4) OUT (n = 2) 3 (GATE="H") GATE OUT (n = 4) Mode 3 CLK WR (n = 4) OUT (GATE="H") GATE OUT (n = 5) 5 (n = 3) 4 4 2 4 2 5 2 4 3 2 2 4 2 4 2 3 2 3 3 5 4 2 5 2
¡ Semiconductor MSM82C53-2RS/GS/JS Reading of Counter Values All MSM82C53-2 counting is down-counting, the counting being in steps of 2 in mode 3. Counter values can be read during counting by (1) direct reading, and (2) counter latching (“read on the fly”). • Direct reading Counter values can be read by direct reading operations.
¡ Semiconductor MSM82C53-2RS/GS/JS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages.
¡ Semiconductor MSM82C53-2RS/GS/JS Differences between MSM82C53-5 and MSM82C53-2 1) Manufacturing Process These devices use a 3 m Si-Gate CMOS process technology and have the same chip size. 2) Function These devices have the same logics except for changes in AC characteristics listed in (3-2).
FEDL82C59A-2-03 FEDL82C59A-2-03 This version: Mar. 2001 MSM82C59A-2RS/GS/JS Previous version: Jan. 1998 ¡ Semiconductor MSM82C59A-2RS/GS/JS ¡ Semiconductor PROGRAMMABLE INTERRUPT CONTROLLER This product is not available in Asia and Oceania. GENERAL DESCRIPTION The MSM82C59A-2 is a programmable interrupt for use in MSM80C85AH and MSM80C86A10/88A-10 microcomputer systems. Based on CMOS silicon gate technology, this device features an extremely low standby current of 100 mA (max.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS BLOCK DIAGRAM INTA D 7 - D0 Data Bus Buffer RD WR A0 Read/ Write Logic CS CAS0 CAS1 CAS2 SP/EN Cascade Buffer/ Comparator INT Control Logic InService Register (ISR) Priority Resolver Interrupt Request Register (IRR) IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 Interrupt Mask Register (IMR) Internal Bus (8 bits) MSM82C59A-2 Internal Block Diagram 2/29
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS PIN CONFIGURATION (TOP VIEW) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC AO INTA IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 INT SP/EN CAS2 28-pin Plastic DIP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC AO INTA NC IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 NC INT SP/EN CAS2 27 AO 28 VCC 1 CS 2 WR 3 RD 4 D7 32-pin Plastic SSOP 26 INTA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D3 8 22 IR4 D2 9 21 IR3 D1 10 20 IR2 D0 1
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply Voltage VCC Input Voltage Output Voltage Storage Temperature VIN Conditions — PD Ta = 25°C Unit MSM82C59A-2RS MSM82C59A-2GS MSM82C59A-2JS Respect to GND VOUT TSTG Power Dissipation Rating –0.5 to +7 V –0.5 to VCC + 0.5 V –0.5 to VCC + 0.5 V °C –55 to +150 0.9 0.7 0.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS AC CHARACTERISTICS Ta = –40°C to +85°C, VCC = 5 V ±10% Parameter Symbol Min. Address Setup Time (to RD) tAHRL 10 — ns Address Hold Time (after RD) tRHAX 5 — ns RD/INTA Pulse Width tRLRH 160 — ns Address Setup Time (to WR) tAHWL 0 — ns Max.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS TIMING CHART Write Timing WR tWLWH tAHWL tWHAX CS Address Bus A0 tDVWH tWHDX Data Bus Read/INTA Timing RD/INTA tRLRH tRLEL EN tRHAX tAHRL CS tRHEH Address Bus A0 tRLDV tRHDZ tAHDV Data Bus Other Timing RD/INTA tRHRL WR tWHWL RD/INTA/WR tCHCL RD/INTA/WR 6/29
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS INTA Sequence (85 mode) IR tJHIH tJLJH INT INTA Data Bus tCVIAL tCVDV CAS Address Bus tIALCV INTA Sequence (86 mode) IR INT INTA Data Bus CAS Address Bus 7/29
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS PIN FUNCTION DESCRIPTION Pin Symbol Name Input/Output D7 - D0 Bidirectional Data Bus Input/Output This 3-state 8-bit bidirectional data bus is used in reading status registers and writing command words through the RD/WR signal from the CPU, and also in reading the CALL instruction code by the INTA signal from the CPU. CS Chip Select Input Input Data transfer with the CPU is enabled by RD/WR when this pin is at low level.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS SYSTEM INTERFACE Address Bus Control Bus Data Bus 8 bits CS A0 CAS0 CAS1 CAS2 Cascade Address Bus D7 - D0 RD WR INT INTA MSM82C59A-2 SP/EN IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 Slave Program/Enable Buffer Interrupt Requests BASIC OPERATION DESCRIPTION Data transfers between the 82C59A-2 internal registers and the data bus are listed below.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS OPERATION DESCRIPTION The MSM82C59A-2 has been designed for real time interrupt driven microcomputer systems. The MSM82C59A-2 is capable of handling up to 8 levels of interrupt requests, and can be expanded to cover a maximum of 64 levels when connected to other MSM82C59A-2 devices. Programming involves the use of system software in the same way as other microcomputer peripheral I/O devices.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS (v) A further two INTA pulses are then sent to the MSM82C59A-2 from the CPU by this CALL instruction. (vi) These two INTA pulses result in a preprogrammed subroutine address being sent from the MSM82C59A-2 to the data bus. The lower 8-bit address is released by the first INTA pulse, and the higher 8-bit address is released by the second pulse.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS Contents of the Second Interrupt vector byte IR Interval = 4 D7 D6 D5 D4 D3 D2 D1 D0 7 A7 A6 A5 1 1 1 0 0 6 A7 A6 A5 1 1 0 0 0 5 A7 A6 A5 1 0 1 0 0 4 A7 A6 A5 1 0 0 0 0 3 2 A7 A6 A5 0 1 1 0 0 A7 A6 A5 0 1 0 0 0 1 A7 A6 A5 0 0 1 0 0 0 A7 A6 A5 0 0 0 0 0 IR Interval = 8 D7 D6 D5 D4 D3 D2 D1 D0 7 A7 A6 1 1 1 0 0 0 6 A7 A6 1 1 0 0 0 0 5 A7 A6 1 0 1
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS Contents of Interrupt Vector Byte in 86 System Mode D7 D6 D5 D4 D3 D2 D1 D0 IR7 T7 T6 T5 T4 T3 1 1 1 IR6 T7 T6 T5 T4 T3 1 1 0 IR5 T7 T6 T5 T4 T3 1 0 1 IR4 T7 T6 T5 T4 T3 1 0 0 IR3 IR2 T7 T6 T5 T4 T3 0 1 1 T7 T6 T5 T4 T3 0 1 0 IR1 T7 T6 T5 T4 T3 0 0 1 IR0 T7 T6 T5 T4 T3 0 0 0 (4) Programming the MSM82C59A-2 The MSM82C59A-2 receives two types of command words generated by the CP
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS (ii) Operation Command Words (OCW1 thru OCW3) These commands are used in operating the MSM82C59A-2 in the following modes. a. Fully Nested Mode b. Rotating Priority Mode c. Special Mask Mode d. Polled Mode The OCW can be written into the MSM82C59A-2 any time after initialization has been completed.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS (ii) Initialization Command Word 3 (ICW3) This command word is written when there is more than one MSM82C59A-2 used in cascade connections in the system, and is loaded into an 8-bit slave register. The functions of this slave register are listed below. a. In a master mode system (BUF = 1 and M/ S = 1 in ICW4 or SP/EN = 1). “1” is set in each bit where a slave has been connected.
FEDL82C59A-2-03 ¡ Semiconductor ICW1 MSM82C59A-2RS/GS/JS A0 D7 D6 D5 D4 D3 D2 D1 D0 0 A7 A6 A5 1 LTIM ADI SNGL IC4 1: ICW4 required 0: ICW4 not required 1: Single 0: Cascade CALL address interval 1: Interval = 4 0: Interval = 8 1: Level triggered mode 0: Edge triggered mode Interrupt vector address A5 thru A7 (Valid only in 85 mode) ICW2 A0 D7 D6 D5 D4 D3 D2 D1 D0 1 A15/T7 A14/T6 A13/T5 A12/T4 A11/T3 A10 A9 A8 Interrupt vector address A8 thru A15 (85 mode) Interrupt
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS (6) Operation Command Words (OCW1 thru OCW3) When Initialization Command Words (ICWs) are programmed in the MSM82C59A-2, the interrupt input line is ready to receive interrupt requests. The Operation Command Words (OCWs) enable the MSM82C59A-2 to be operated in various modes while the device is in operation. (i) Operation Command Word 1 (OCW1) OCW1 sets and resets the mask bits of the Interrupt Mask Register (IMR). M0 thru M7 represent 8 mask bits.
FEDL82C59A-2-03 ¡ Semiconductor OCW1 MSM82C59A-2RS/GS/JS A0 D7 D6 D5 D4 D3 D2 D1 D0 1 M7 M6 M5 M4 M3 M2 M1 M0 Interrupt Mask 1: Mask set 0: Mask reset OCW2 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 R SL EOI 0 0 L2 L1 L0 Active IR Level 0 0 1 Non-specific EOI command 0 1 1 Specific EOI command (NOTE) 1 0 1 Rotate on non-specific EOI command 1 0 0 Rotate in automatic EOI mode (SET) 0 0 0 Rotate in automatic EOI mode (Clear) 1 1 1 Rotate on specific EOI comman
FEDL82C59A-2-03 ¡ Semiconductor (7) MSM82C59A-2RS/GS/JS Fully Nested Mode As long as the MSM82C59A-2 has not been programmed to another mode, this Fully Nested mode is set automatically after initialization. The interrupt requests are ordered in priority sequentially from 0 to 7 (where 0 represents highest priority). If an interrupt is then requested and is acknowledged highest priority, a corresponding vector address is released, and the corresponding bit in the in-service register (ISR) is set.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS Before Rotation (IR4 the highest priority requesting service) IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0 IS Status 0 1 0 1 0 0 0 0 Priority Status 7 6 5 4 3 2 1 0 Lowest Highest After Rotation (IR4 was serviced, all other priorities rotated correspondingly) IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0 IS Status 0 1 0 0 0 0 0 0 Priority Status 2 1 0 7 6 5 4 3 Highest Lowest (11) Specific Rotation (Specific Priority) All priority levels can
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS (13) Special Mask Mode In some applications, there is a need for dynamic updating of the system’s priority level structure by software control during execution of an interrupt service routine. For example, it may be necessary to inhibit the lower priority requests for part of the execution of a certain routine while enabling for another part.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS (15) Reading MSM82C59A-2 Status The status of a number of internal registers can be read out for updating user information on the system. The following registers can be read by means of OCW3 (IRR and ISR) and OCW1 (IMR). a. IRR: (Interrupt Request Register) 8-bit register for storing interrupt requesting levels. b. ISR: (In-Service Register) 8-bit register for storing priority levels being serviced. c.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS (17) Special Fully Nested Mode This mode is used in large systems where the cascade mode is used and the respective Interrupt Requests within each slave have to be given priority levels. In this case, the Special Fully Nested mode is programmed to the master by using ICW4. This mode is practically identical to the normal Fully Nested mode, but differs in the following two respects. a.
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS Address Bus Control Bus Data Bus Cascade Bus CS A0 D0 - 7 INTA MSM82C59A-2 CAS0 - 2 INT SP/EN (Slave) 7 6 5 4 3 2 1 0 GND 7 6 5 4 3 2 1 0 CS A0 D0 - 7 INTA MSM82C59A-2 CAS0 - 2 INT SP/EN (Slave) 7 6 5 4 3 2 1 0 GND VCC 7 6 5 4 3 2 1 0 CS A0 D0 - 7 INTA CAS0 - 2 MSM82C59A-2 INT SP/EN (Master) M7 M6 M5 M4 M3 M2 M1 M0 7 5 4 2 1 0 Interrupt Requests MSM82C59A-2 Cascade Connections 24/29
FEDL82C59A-2-03 ¡ Semiconductor MSM82C59A-2RS/GS/JS Precautions for operation Contents: In the case of a cascade edge trigger, the low level width (TILIH) of a slave INT signal may be less than the low level width (TJLJH:100 ns min.) of a master IR input signal. This occurs when an interruption request with high order priority is provided to the slave unit before the INTA cycle ends. Fig.1 shows a system configuration, Fig.2 a bug operation timing chart, and Fig.3 a normal operation timing chart.
E2O0017-27-X2 This version: Jan. 1998 MSM82C51A-2RS/GS/JS Previous version: Aug. 1996 ¡ Semiconductor MSM82C51A-2RS/GS/JS ¡ Semiconductor UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER This product is not available in Asia and Oceania. GENERAL DESCRIPTION The MSM82C51A-2 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication.
¡ Semiconductor MSM82C51A-2RS/GS/JS D7 - D0 Data Bus Buffer RESET CLK C/D RD WR CS Read/Write Control Logic DSR DTR CTS RTS Modem Control Internal Bus Line FUNCTIONAL BLOCK DIAGRAM Transmit Buffer (P - S) TXD Transmit Control TXRDY TXE TXC Recieve Buffer (S - P) RXD Recieve Control RXRDY RXC SYNDET/BD 2/26
¡ Semiconductor MSM82C51A-2RS/GS/JS PIN CONFIGURATION (TOP VIEW) 28 pin Plastic DIP 1 28 D1 D3 2 27 D0 RXD 3 26 VCC GND 4 25 RXC D4 5 24 DTR D5 6 23 RTS D6 7 22 DSR D7 8 21 RESET TXC 9 20 CLK WR 10 19 TXD 18 TXEMPTY 26 VCC 27 D0 28 D1 1 D2 CS 11 2 D3 3 RXD 4 GND 28 pin Plastic QFJ D2 C/D 12 17 CTS RD 13 16 SYNDET/BD 15 TXRDY RXRDY 14 D4 5 25 RXC D5 6 24 DTR D6 7 23 RTS D7 8 22 DSR TXC 9 21 RESET D2 1 32 D1 18 32 pin Plastic SSOP D3 2 31 D0
¡ Semiconductor MSM82C51A-2RS/GS/JS FUNCTION Outline The MSM82C51A-2's functional configuration is programed by software. Operation between the MSM82C51A-2 and a CPU is executed by program control. Table 1 shows the operation between a CPU and the device.
¡ Semiconductor MSM82C51A-2RS/GS/JS Control Words There are two types of control word. 1. Mode instruction (setting of function) 2. Command (setting of operation) 1) Mode Instruction Mode instruction is used for setting the function of the MSM82C51A-2. Mode instruction will be in “wait for write” at either internal reset or external reset. That is, the writing of a control word after resetting will be recognized as a “mode instruction.
¡ Semiconductor MSM82C51A-2RS/GS/JS D7 D6 D5 D4 D3 D2 D1 D0 SCS ESD EP PEN L2 L1 0 0 Charactor Length 0 1 0 1 0 0 1 1 5 bits 6 bits 7 bits 8 bits 0 1 0 1 0 0 Odd Parity 1 1 Even Parity Parity Disable Disable Synchronous Mode 0 1 Internal Synchronization External Synchronization Number of Synchronous Charactors 0 1 2 Charactors 1 Charactor Fig.
¡ Semiconductor MSM82C51A-2RS/GS/JS 2) Command Command is used for setting the operation of the MSM82C51A-2. It is possible to write a command whenever necessary after writing a mode instruction and sync characters. Items to be set by command are as follows: • • • • • • • Transmit Enable/Disable Receive Enable/Disable DTR, RTS Output of data. Resetting of error flag. Sending to break characters Internal resetting Hunt mode (synchronous mode) The bit configuration of a command is shown in Fig. 4.
¡ Semiconductor MSM82C51A-2RS/GS/JS Status Word It is possible to see the internal status of MSM82C51A-2 by reading a status word. The bit configuration of status word is shown in Fig. 5. D7 D6 D5 D4 D3 D2 D1 D0 DSR SYNDET /BD FE OE PE TXEMPTY RXRDY TXRDY Parity Different from TXRDY Terminal. Refer to "Explanation" of TXRDY Terminals. Same as terminal. Refer to "Explanation" of Terminals. 1ºParity Error 1ºOverrun Error 1ºFraming Error Note: Only asynchronous mode.
¡ Semiconductor MSM82C51A-2RS/GS/JS Pin Description D0 to D7 (l/O terminal) This is bidirectional data bus which receive control words and transmits data from the CPU and sends status words and received data to CPU. RESET (Input terminal) A “High” on this input forces the MSM82C51A-2 into “reset status.” The device waits for the writing of “mode instruction.” The min. reset width is six clock inputs during the operating status of CLK.
¡ Semiconductor MSM82C51A-2RS/GS/JS TXRDY (output terminal) This is an output terminal which indicates that the MSM82C51A-2 is ready to accept a transmitted data character. But the terminal is always at low level if CTS = high or the device was set in “TX disable status” by a command. Note: TXRDY status word indicates that transmit data character is receivable, regardless of CTS or command. If the CPU writes a data character, TXRDY will be reset by the leading edge or WR signal.
¡ Semiconductor MSM82C51A-2RS/GS/JS SYNDET/BD (Input or output terminal) This is a terminal whose function changes according to mode. In “internal synchronous mode.” this terminal is at high level, if sync characters are received and synchronized. If a status word is read, the terminal will be reset. In “external synchronous mode, “this is an input terminal. A “High” on this input forces the MSM82C51A-2 to start receiving data characters.
¡ Semiconductor MSM82C51A-2RS/GS/JS ABSOLUTE MAXIMUM RATING Parameter Rating Symbol Unit Conditions MSM82C51A-2RS MSM82C51A-2GS MSM82C51A-2JS Power Supply Voltage VCC –0.5 to +7 V Input Voltage VIN –0.5 to VCC +0.5 V VOUT TSTG –0.5 to VCC +0.5 V Output Voltage Storage Temperature Power Dissipation –55 to +150 0.9 PD 0.7 0.
¡ Semiconductor MSM82C51A-2RS/GS/JS AC CHARACTERISTICS CPU Bus Interface Part (VCC = 4.5 to 5.5 V, Ta = –40 to 85°C) tAR Min. 20 Max.
¡ Semiconductor MSM82C51A-2RS/GS/JS Serial Interface Part (VCC = 4.5 to 5.
¡ Semiconductor MSM82C51A-2RS/GS/JS TIMING CHART Sytem Clock Input tf tr tf tf tCY CLK Transmitter Clock and Data tTPW TXC (1 ¥ MODE) tTPD TXC (16 ¥ MODE) tDTX tDTX TXD Receiver Clock and Data RXD RXC (1 ¥ Mode) RXC (16 ¥ Mode) (RXBAUD Counter starts here) Start bit tRPW 8RXC Periods (16¥Mode) Data bit 16 RXC Periods (16 ¥ Mode) 3tCY INT Sampling Pulse Data bit tRPD 3tCY tf 15/26
¡ Semiconductor MSM82C51A-2RS/GS/JS Write Data Cycle (CPU Æ USART) TXRDY tWW WR DATA IN (D. B.) tTXRDY Clear tWD tDW Don't Care Don't Care Data Stable C/D tAW tWA CS tAW tWA Read Data Cycle (CPU ¨ USART) RXRDY tRXRDY Clear tRR RD DATA OUT (D. B.) tRD Data Float tDF Data Float Data Out Active C/D tAR tRA CS tAR tRA Write Control or Output Port Cycle (CPU Æ USART) DTR. RTS DATA IN (D. B.
¡ Semiconductor MSM82C51A-2RS/GS/JS Transmitter Control and Flag Timing (ASYNC Mode) CTS tTXEMPTY TXEMPTY TXRDY (STATUS BIT) tTXRDY TXRDY (PIN) Wr DATA 1 Wr DATA 2 Wr DATA 3 Wr DATA 4 C/D Wr TxEn Wr SBRK WR 0 1 2 3 4 5 6 TXD DATA CHAR 2 DATA CHAR 3 DATA CHAR 4 STOP BIT START BIT DATA CHAR 1 Note: The wave-form chart is based on the case of 7-bit data length + parity bit + 2 stop bit.
¡ Semiconductor MSM82C51A-2RS/GS/JS Receiver Control and Flag Timing (SYNC Mode) (Note 2) SYNDET (Pin) (Note 1) tES tIS SYNDET (SB) OVERRUN ERROR (SB) Data CHAR2 Lost RXRDY (PIN) Rd Status C/D Wr EH RxEn Wr Err Res Rd Data CHAR 1 Rd Data CHAR 3 Rd Status Rd Status Wr EHo Rd SYNC CHAR 1 WR RD Don't Care RXD SYNC CHAR 1 SYNC CHAR 2 Data CHAR 1 Data CHAR 2 Data CHAR 3 SYNC CHAR 1 SYNC CHAR 2 Don't Care Data CHAR 1 Data CHAR 2 x x x x x x 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1
¡ Semiconductor MSM82C51A-2RS/GS/JS Half-bit Processing Timing Chart for the Start bit (Fig. 1) Normal Operation RXD ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RXRDY The Start bit Is Shorter Than a 1/2 Data bit ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RXD ST RXRDY The Start bit Is a 1/2 Data bit (A problem of MSM82C51A-2) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RXD ST RXRDY A RXRDY signal is outputted during data reception due to a malfunction.
¡ Semiconductor MSM82C51A-2RS/GS/JS Break Signal Reception Timing and Parity Flag (Fig. 2) Normal Operation BIT POS. ST D0 D7 P SP ST D0 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RXD RXRDY ≠ No parity flag is set. and no RXRDY signal is outputted. Bug Timing BIT POS. ST D0 D7 P SP ST D0 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RXD RXRDY ≠ A parity flag is set, but, no RXRDYsignal is outputted. Normal Operation BIT POS.
¡ Semiconductor MSM82C51A-2RS/GS/JS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages.
¡ Semiconductor MSM82C51A-2RS/GS/JS Differences between MSM82C51A and MSM82C51A-2 1) Manufacturing Process These devices use a 3 m Si-Gate CMOS process technology and have the same chip size. 2) Function These devices have the same logics except for changes in AC characteristics listed in (3-2). 3) Electrical Characteristics 3-1) DC Characteristics Parameter Symbol MSM82C51A MSM82C51A-2 VOL measurement conditions IOL +2.0 mA +2.5 mA VOH measurement conditions IOH -400 mA -2.
