User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 6: IP Core Architecture 6–23
Single DWord Completer Endpoint
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Figure 6–13 shows Qsys system that includes a completer-only single dword
endpoint.
As Figure 6–13 illustrates, the completer-only single dword Endpoint connects to PCI
Express Root Complex. A bridge component includes the Cyclone V Hard IP for PCI
Express TX and RX blocks, an Avalon-MM RX master, and an interrupt handler. The
bridge connects to the FPGA fabric using an Avalon-MM interface. The following
sections provide an overview of each block in the bridge.
RX Block
The RX Block control logic interfaces to the hard IP block to respond to requests from
the root complex. It supports memory reads and writes of a single dword. It generates
a completion with Completer Abort (CA) status for read requests greater than four
bytes and discards all write data without further action for write requests greater than
four bytes.
The RX block passes header information to the Avalon-MM master, which generates
the corresponding transaction to the Avalon-MM interface. The bridge accepts no
additional requests while a request is being processed. While processing a read
request, the RX block deasserts the
ready
signal until the TX block sends the
corresponding completion packet to the hard IP block. While processing a write
request, the RX block sends the request to the Avalon-MM interconnect fabric before
accepting the next request.
Avalon-MM RX Master Block
The 32-bit Avalon-MM master connects to the Avalon-MM interconnect fabric. It
drives read and write requests to the connected Avalon-MM slaves, performing the
required address translation. The RX master supports all legal combinations of byte
enables for both read and write requests.
Figure 6–13. Qsys Design Including Completer Only Single DWord Endpoint for PCI Express
Qsys System
PCI Express
Root Complex
PCIe Link
to Host
CPU
Avalon-MM
Interconnect
Fabric
Avalon-MM
Slave
Avalon-MM
Slave
Avalon-MM
Hard IP
for PCIe
Avalon-MM
Master RX
Interrupt
Handler
RX Block
TX Block
Completer Only Single DWord Endpoint
Qsys Component
.
.
.
Bridge