User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
6–20 Chapter 6: IP Core Architecture
Avalon-MM Bridge TLPs
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
This design is consuming 1.25GB of PCIe address space when only 276 MBytes are
actually required. The solution is to edit the address map to place the base address of
each BAR at 0x0000_0000. Figure 6–10 illustrates the optimized address map.
h For more information about changing Qsys addresses using the Qsys address map,
refer to Address Map Tab (Qsys) in Quartus II Help.
Figure 6–11 shows the number of address bits required when the smaller memories
accessed by BAR2 and BAR4 have a base address of 0x0000_0000.
For cases where the BAR Avalon-MM RX master port connects to more than one
Avalon-MM slave, assign the base addresses of the slaves sequentially and place the
slaves in the smallest power-of-two-sized address space possible. Doing so minimizes
the system address space used by the BAR.
Avalon-MM-to-PCI Express Address Translation Algorithm
The Avalon-MM address of a received request on the TX Slave Module port is
translated to the PCI Express address before the request packet is sent to the
Transaction Layer. You can specify up to 512 address pages and sizes ranging from
4 KByte to 4 GBytes when you customize your Avalon-MM Cyclone V Hard IP for
PCI Express as described in “Avalon to PCIe Address Translation Settings” on
page 5–10. This address translation process proceeds by replacing the MSB bits of the
Avalon-MM address with the value from a specific translation table entry; the LSB bits
remains unchanged. The number of MSBs to be replaced is calculated based on the
total address space of the upstream PCI Express devices that the Avalon-MM Hard IP
for PCI Express can access.
The address translation table contains up to 512 possible address translation entries
that you can configure. Each entry corresponds to a base address of the PCI Express
memory segment of a specific size. The segment size of each entry must be identical.
The total size of all the memory segments is used to determine the number of address
MSB bits to be replaced. In addition, each entry has a 2-bit field,
Sp[1:0]
, that
Figure 6–10. Optimized Address Map
Figure 6–11. Reduced Address Bits for BAR2 and BAR4