User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 6: IP Core Architecture 6–17
Avalon-MM Bridge TLPs
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
PCI Express-to-Avalon-MM Address Translation for Endpoints
The PCI Express Avalon-MM Bridge translates the system-level physical addresses,
typically up to 64 bits, to the significantly smaller addresses used by the Application
Layer’s Avalon-MM slave components. You can specify up to six BARs for address
translation when you customize your Hard IP for PCI Express as described in “Base
Address Registers for Function <n>” on page 4–8. The PCI Express Avalon-MM
Bridge also translates the Application Layer addresses to system-level physical
addresses as described in “Avalon-MM-to-PCI Express Address Translation
Algorithm” on page 6–20.
Figure 6–7 provides a high-level view of address translation in both directions.
1 When configured as a Root Port, a single RX Avalon-MM master forwards all RX TLPs
to the Qsys interconnect.
The Avalon-MM RX master module port has an 8-byte datapath in 64-bit mode and a
16-byte datapath in 128-bit mode. The Qsys interconnect fabric manages mismatched
port widths transparently.
As Memory Request TLPs are received from the PCIe link, the most significant bits are
used in the BAR matching as described in the PCI specifications. The least significant
bits not used in the BAR match process are passed unchanged as the Avalon-MM
address for that BAR's RX Master port.
For example, consider the following configuration specified using the Base Address
Registers in the GUI.
1. BAR1:0 is a 64-bit prefetchable memory that is 4KBytes -12 bits
Figure 6–7. Address Translation in TX and RX Directions
Transaction,
Data Link,
and PHY
DMA
Avalon-MM
32-Bit Byte Address
Avalon-MM
32-Bit Byte Address
PCIe TLP
Address
PCIe TLP
Address
Qsys Generated Endpoint with DMA Controller and On-Chip RAM
TX
PCIe
Link
RX
PCIe
Link
PCI Express Avalon-MM Bridge
Interconnect
Avalon-MM Hard IP for PCI Express
Number of address pages (1-512)
Size of address pages
Address Translation Table Parameters
Avalon-MM-to-PCIe Address Translation
BAR (0-5)
BAR Type
BAR Size
PCI Base Address Registers (BAR)
PCIe-to-Avalon-MM Address Translation
On-
Chip
RAM
M
S
= RX Avalon-MM Master
= TX Avalon-MM Slave
S M