User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
6–10 Chapter 6: IP Core Architecture
Protocol Layers
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Figure 6–5 illustrates the Physical Layer architecture.
The Physical Layer is subdivided by the PIPE Interface Specification into two layers
(bracketed horizontally in Figure 6–5):
■ Media Access Controller (MAC) Layer—The MAC layer includes the LTSSM and
the scrambling/descrambling and multilane deskew functions.
■ PHY Layer—The PHY layer includes the 8B/10B encode/decode functions, elastic
buffering, and serialization/deserialization functions.
The Physical Layer integrates both digital and analog elements. Intel designed the
PIPE interface to separate the MAC from the PHY. The Cyclone V Hard IP for PCI
Express complies with the PIPE interface specification.
The PHYMAC block is divided in four main sub-blocks:
■ MAC Lane—Both the RX and the TX path use this block.
■ On the RX side, the block decodes the Physical Layer Packet and reports to the
LTSSM the type and number of TS1/TS2 ordered sets received.
■ On the TX side, the block multiplexes data from the DLL and the LTSTX
sub-block. It also adds lane specific information, including the lane number
and the force PAD value when the LTSSM disables the lane during
initialization.
Figure 6–5. Physical Layer
Scrambler
8B10B
Encoder
Lane n
Tx+ / Tx-
Scrambler
8B10B
Encoder
Lane 0
Tx+ / Tx-
Descrambler
8B10B
Decoder
Lane n
Rx+ / Rx-
Elastic
Buffer
LTSSM
State Machine
SKIP
Generation
Control & Status
PIPE
Emulation Logic
Link Serial izer
Link Serial izer
Tx Packets
Rx MAC
Lane
Device Transceiver (per Lane) with 2.5 or 5.0 Gbps SERDES & PLL
Descrambler
8B10B
Decoder
Lane 0
Rx+ / Rx-
Elastic
Buffer
Rx MAC
Lane
PIPE
Interface
Multilane Deskew
Rx Packets
Transmit
Data Path
Receive
Data Path
MAC Layer PHY layer
To LinkTo Data Link Layer