User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 6: IP Core Architecture 6–7
Protocol Layers
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
2. The Application Layer requests permission to transmit a TLP. The Application
Layer must provide the transaction and must be prepared to provide the entire
data payload in consecutive cycles.
3. The Transaction Layer verifies that sufficient flow control credits exist and
acknowledges or postpones the request.
4. The Transaction Layer forwards the TLP to the Data Link Layer.
Configuration Space
The Configuration Space implements the following Configuration Space Registers
and associated functions:
■ Header Type 0 Configuration Space for Endpoints
■ Header Type 1 Configuration Space for Root Ports
■ MSI Capability Structure
■ MSI-X Capability Structure
■ PCI Power Management Capability Structure
■ PCI Express Capability Structure
■ SSID / SSVID Capability Structure
■ Virtual Channel Capability Structure
■ Advance Error Reporting Capability Structure
The Configuration Space also generates all messages (PME#, INT, error, slot power
limit), MSI requests, and completion packets from configuration requests that flow in
the direction of the root complex, except slot power limit messages, which are
generated by a downstream port. All such transactions are dependent upon the
content of the PCI Express Configuration Space as described in the PCI Express Base
Specification Revision 2.1.
Refer To “Configuration Space Register Content” on page 8–1 or Chapter 7 in the PCI
Express Base Specification 2.1 for the complete content of these registers.
Data Link Layer
The Data Link Layer is located between the Transaction Layer and the Physical Layer.
It maintains packet integrity and communicates (by DLL packet transmission) at the
PCI Express link level (as opposed to component communication by TLP
transmission in the interconnect fabric).
The DLL implements the following functions:
■ Link management through the reception and transmission of DLL packets (DLLP),
which are used for the following functions:
■ For power management of DLLP reception and transmission
■ To transmit and receive
ACK
/
NACK
packets
■ Data integrity through generation and checking of CRCs for TLPs and DLLPs
■ TLP retransmission in case of
NAK
DLLP reception using the retry buffer