User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
6–4 Chapter 6: IP Core Architecture
Key Interfaces
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
credits become available. By tracking the credit consumed information and
calculating the credits available, the Application Layer can optimize performance by
selecting for transmission only the TLPs that have credits available. for more
information about the signals in this interface, refer to “Avalon-ST TX Interface” on
page 7–15 Avalon-MM Interface
In Qsys, the Cyclone V Hard IP for PCI Express is available with either an Avalon-ST
interface or an Avalon-MM interface to the Application Layer. When you select the
Avalon-MM Cyclone V Hard IP for PCI Express, an Avalon-MM bridge module
connects the PCI Express link to the system interconnect fabric. If you are not familiar
with the PCI Express protocol, variants using the Avalon-MM interface may be easier
to understand. A PCI Express to Avalon-MM bridge translates the PCI Express read,
write and completion TLPs into standard Avalon-MM read and write commands
typically used by master and slave interfaces. The PCI Express to Avalon-MM bridge
also translates Avalon-MM read, write and read data commands to PCI Express read,
write and completion TLPs.
Clocks and Reset
The PCI Express Base Specification requires an input reference clock, which is called
refclk
in this design. Although the PCI Express Base Specification stipulates that the
frequency of this clock be 100 MHz, the Hard IP also accepts a 125 MHz reference
clock as a convenience. You can specify the frequency of your input reference clock
using the parameter editor under the System Settings heading.
The PCI Express Base Specification 2.1, requires the following three reset types:
■ cold reset—A hardware mechanism for setting or returning all port states to the
initial conditions following the application of power.
■ warm reset—A hardware mechanism for setting or returning all port states to the
initial conditions without cycling the supplied power.
■ hot reset —A reset propagated across a PCIe link using a Physical Layer
mechanism.
The PCI Express Base Specification also requires a system configuration time of 100 ms.
To meet this specification, the Cyclone V Hard IP for PCI Express includes an
embedded hard reset controller. For more information about clocks and reset, refer to
the “Clock Signals” on page 7–23 and “Reset Signals” on page 7–24.
Local Management Interface (LMI Interface)
The LMI bus provides access to the PCI Express Configuration Space in the
Transaction Layer. For information about the LMI interface, refer to “LMI Signals” on
page 7–38.