User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 5: Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express 5–9
Avalon Memory-Mapped System Settings
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Avalon Memory-Mapped System Settings
Table 5–10 lists the Avalon-MM system parameter registers.
Table 5–10. Avalon Memory-Mapped System Settings
Parameter Value Description
Avalon-MM data
width
64-bit
128-bit
Specifies the interface width between the PCI Express Transaction Layer
and the Application Layer. Refer to Table 9–2 on page 9–6 for a
comprehensive list of available link width, interface width, and frequency
combinations.
Peripheral Mode
Requester/Completer,
Completer-Only
Specifies whether the Avalon-MM Cyclone V Hard IP for PCI Express is
capable of sending requests to the upstream PCI Express devices.
Requester/Completer—In this mode, the Hard IP can send request
packets on the PCI Express TX link and receive request packets on the
PCI Express RX link.
Completer-Only—In this mode, the Hard IP can receive requests, but
cannot initiate upstream requests. However, it can transmit completion
packets on the PCI Express TX link. This mode removes the Avalon-MM
TX slave port and thereby reduces logic utilization.
Single DW completer On/Off
This is a non-pipelined version of Completer-Only mode. At any time, only
a single request can be outstanding. Single dword completer uses fewer
resources than Completer-Only. This variant is targeted for systems that
require simple read and write register accesses from a host CPU. If you
select this option, the width of the data for RXM BAR masters is always 32
bits, regardless of the Avalon-MM width.
Control Register
Access (CRA)
Avalon-MM slave
port
On/Off
Allows read and write access to bridge registers from the interconnect
fabric using a specialized slave port. This option is required for
Requester/Completer variants and optional for Completer-Only variants.
Enabling this option allows read and write access to bridge registers. This
option is not available for the Single dword completer.
Enable multiple
MSI/MSI-X support
On/Off
When you turn this option On, the core includes top-level MSI and MSI-X
interfaces that you can use to implement a Customer Interrupt Handler for
MSI and MSI-X interrupts. For more information about the Custom
Interrupt Handler, refer to Interrupts for End Points Using the Avalon-MM
Interface with Multiple MSI/MSI-X Support.
Auto Enable PCIe
interrupt (enabled at
power-on)
On/Off
Turning on this option enables the Avalon-MM Cyclone V Hard IP for PCI
Express interrupt register at power-up. Turning off this option disables the
interrupt register at power-up. The setting does not affect run-time
configuration of the interrupt enable register.