User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 4: Parameter Settings for the Cyclone V Hard IP for PCI Express 4–5
Port Functions
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Error Reporting
Table 4–3 describes the Advanced Error Reporting (AER) and ECRC parameters.
These parameters are supported only in single function mode.
Completion
timeout range
(continued)
The following encodings are used to specify the range:
■ 0001 Range A
■ 0010 Range B
■ 0011 Ranges A and B
■ 0110 Ranges B and C
■ 0111 Ranges A, B, and C
■ 1110 Ranges B, C and D
■ 1111 Ranges A, B, C, and D
All other values are reserved. Altera recommends that the
completion timeout mechanism expire in no less than 10 ms.
Implement
completion
timeout disable
On/Off On
Sets the value of the Completion Timeout field of the
Device
Control 2
register (0x0A8) which is For PCI Express
version 2.0 and higher Endpoints, this option must be On. The
timeout range is selectable. When On, the core supports the
completion timeout disable mechanism via the PCI Express
Device Control Register 2
. The Application Layer logic
must implement the actual completion timeout mechanism
for the required ranges.
Table 4–2. Capabilities Registers for Function <n> (Part 2 of 2)
Parameter
Possible
Values
Default
Value
Description
Table 4–3. Error Reporting 0x800–0x834
Parameter Value
Default
Value
Description
Advanced error
reporting (AER)
On/Off Off When On, enables the AER capability.
ECRC checking On/Off Off
When On, enables ECRC checking. Sets the read-only value of the
ECRC check capable bit in the
Advanced Error Capabilities
and Control Register
. This parameter requires you to enable the
AER capability.
ECRC generation On/Off Off
When On, enables ECRC generation capability. Sets the read-only
value of the ECRC generation capable bit in the
Advanced Error
Capabilities and Control Register
. This parameter requires
you to enable the AER capability.
ECRC forwarding On/Off Off
When On, enables ECRC forwarding to the Application Layer. On the
Avalon-ST RX path, the incoming TLP contains the ECRC dword
(1)
and the
TD
bit is set if an ECRC exists. On the transmit the TLP from
the Application Layer must contain the ECRC dword and have the
TD
bit set.
Note to Table 4–3:
(1) Throughout The Cyclone V Hard IP for PCI Express User Guide, the terms word, dword and qword have the same meaning that they have in the
PCI Express Base Specification Revision 2.1. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.