User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
4. Parameter Settings for the Cyclone V
Hard IP for PCI Express
This chapter describes the parameters which you can set using the MegaWizard
Plug-In Manager or Qsys design flow to instantiate a Cyclone V Hard IP for PCI
Express IP core. The appearance of the GUI is identical for the two design flows.
1 In the following tables, hexadecimal addresses in green are links to additional
information in the “Register Descriptions” chapter.
System Settings
The first group of settings defines the overall system. Table 4–1 describes these
settings.9
Table 4–1. System Settings for PCI Express (Part 1 of 3)
Parameter Value Description
Number of Lanes ×1, ×2, ×4 Specifies the maximum number of lanes supported.
Lane Rate
Gen1 (2.5 Gbps)Gen2
(2.5/5.0 Gbps)
Specifies the maximum data rate at which the link can operate.
Cyclone V GX supports Gen1 ×1 and ×4
Cyclone V GT supports Gen1 ×1 and ×4, and Gen2 ×1 and ×4
Port type
Native Endpoint
Root Port
Legacy Endpoint
Specifies the function of the port. Altera recommends Native Endpoint
for all new Endpoint designs. Select Legacy Endpoint only when you
require I/O transaction support for compatibility.
The Endpoint stores parameters in the Type 0 Configuration Space which
is outlined in Table 8–2 on page 8–2. The Root Port stores parameters in
the Type 1 Configuration Space which is outlined n Table 8–3 on
page 8–2.
Application Interface
64-bit Avalon-ST128-
bit Avalon-ST
Specifies the interface between the PCI Express Transaction Layer and
the Application Layer. Refer to Table 9–2 on page 9–6 for a
comprehensive list of available link width, interface width, and frequency
combinations.
December 2013
UG-01110-1.5