User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
3–10 Chapter 3: Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
Specifying Address Assignments
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Specifying Address Assignments
Qsys requires that you resolve the base addresses of all Avalon-MM slave interfaces in
the Qsys system. You can either use the auto-assign feature, or specify the base
addresses manually. To use the auto-assign feature, on the System menu, click Assign
Base Addresses. In the design example, you assign the base addresses manually.
The Avalon-MM Cyclone Hard IP for PCI Express assigns base addresses to each
BAR. The maximum supported BAR size is 4 GByte, or 32 bits.
Follow these steps to assign a base address to an Avalon-MM slave interface
manually:
1. In the row for the Avalon-MM slave interface base address you want to specify,
click the Base column.
2. Type your preferred base address for the interface.
3. Assign the base addresses listed in Table 3–13.
The following figure illustrates the complete system.
For this example BAR1:0 is 22 bits or 4 MBytes. This BAR accesses Avalon addresses
from 0x00200000– 0x00200FFF. BAR2 is 15 bits or 32 KBytes. BAR2 accesses the DMA
control_port_slave at offsets 0x00004000 through 0x0000403F. The pci_express
CRA
slave port is accessible at offsets 0x0000000–0x0003FFF from the programmed BAR2
base address. For more information on optimizing BAR sizes, refer to “Minimizing
BAR Sizes and the PCIe Address Space” on page 7–21.
Simulating the Example Design
Follow these steps to generate the files for the testbench and synthesis.
1. On the Generation tab, in the Simulation section, set the following options:
a. For Create simulation model, select None. (This option allows you to create a
simulation model for inclusion in your own custom testbench.)
b. For Create testbench Qsys system, select Standard, BFMs for standard
Avalon interfaces.
c. For Create testbench simulation model, select Ve ri lo g.
2. In the Synthesis section, turn on Create HDL design files for synthesis.
3. Click the Generate button at the bottom of the tab.
Table 3–13. Base Address Assignments for Avalon-MM Slave Interfaces
Interface Name Exported Name
DUT
Txs 0x00000000
DUT
Cra 0x00000000
DMA
control_port_slave 0x00004000
onchip_memory_0
s1 0x00200000