User guide

3–8 Chapter 3: Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
Completing the Connections in Qsys
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
12. Click Finish.
13. The Transceiver Reconfiguration Controller is added to your Qsys system.
f For more information about the Transceiver Reconfiguration Controller, refer to the
Transceiver Reconfiguration Controller chapter in the Altera Transceiver PHY IP Core User
Guide.
Completing the Connections in Qsys
In Qsys, hovering the mouse over the Connections column displays the potential
connection points between components, represented as dots on connecting wires. A
filled dot shows that a connection is made; an open dot shows a potential connection
point. Clicking a dot toggles the connection status. If you make a mistake, you can
select Undo from the Edit menu or type
Ctrl-z .
By default, Qsys filters some interface types to simplify the image shown on the
System Contents tab. Complete these steps to display all interface types:
1. Click the Filter tool bar button.
2. In the Filter list, select All interfaces.
3. Close the Filters dialog box.
To complete the design, create the following connections:
1. Connect the pcie_sv_hip_avmm_0
Rxm_BAR0 Avalon Memory-Mapped Master port
to the onchip_memory2_0
s1 Avalon Memory-Mapped slave port using the
following procedure:
a. Click the
Rxm_BAR0 port, then hover in the Connections column to display
possible connections.
b. Click the open dot at the intersection of the
onchip_mem2_0 s1 port and the
pci_express_compiler
Rxm_BAR0 to create a connection.
2. Repeat step 1 to make the connections listed in Table 3–11.
Table 3–11. Qsys Connections (Part 1 of 2)
Make Connection From: To:
DUT
nreset_status Reset Output onchip_memory reset1 Avalon slave port
DUT
nreset_status Reset Output dma_0 reset Reset Input
DUT
nreset_status Reset Output alt_xcvr_reconfig_0 mgmt_rst_reset Reset Input
DUT
Rxm_BAR0 Avalon Memory Mapped Master onchip_memory s1 Avalon slave port
DUT
Rxm_BAR2 Avalon Memory Mapped Master DUT Cra Avalon Memory Mapped Slave
DUT
Rxm_BAR2 Avalon Memory Mapped Master
dma_0
control_port_slave Avalon Memory Mapped
Slave
DUT
RxmIrq Interrupt Receiver dma_0 irq Interrupt Sender
DUT
reconfig_to_xcvr Conduit alt_xcvr_reconfig_0 reconfig_to_xcvr Conduit
DUT
reconfig_busy Conduit alt_xcvr_reconfig_0 reconfig_busy Conduit
DUT
reconfig_from_xcvr Conduit alt_xcvr_reconfig_0 reconfig_from_xcvr Conduit
DUT
Txs Avalon Memory Mapped Slave dma_0 read_master Avalon Memory Mapped Master