User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 3: Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express 3–5
Adding the Remaining Components to the Qsys System
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
5. Under the Avalon-MM System Settings heading, specify the settings in Table 3–6.
6. Under the Avalon-MM to PCI Express Address Translation Settings, specify the
settings in Table 3–7.
Refer to “Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit
Addressing” on page 7–23 for more information about address translation.
7. Click Finish.
8. To rename the Cyclone Hard IP for PCI Express, in the Name column of the
System Contents tab, right-click on the component name, select Rename, and
type
DUT
r
1 Your system is not yet complete, so you can ignore any error messages generated by
Qsys at this stage.
1 Qsys displays the values for Posted header credit, Posted data credit, Non-posted
header credit, Completion header credit, and Completion data credit in the message
area. These values are computed based upon the values set for Maximum payload
size and Desired performance for received requests.
Adding the Remaining Components to the Qsys System
This section describes adding the DMA controller and on-chip memory to your
system.
1. On the Component Library tab, type the following text string in the search box:
DMA r
Qsys filters the component library and shows all components matching the text
string you entered.
2. Click DMA Controller and then click +Add. This component contains read and
write master ports and a control port slave.
Table 3–6. Avalon Memory-Mapped System Settings
Parameter Value
Avalon-MM width 64 bits
Peripheral Mode Requester/Completer
Single DWord Completer Off
Control register access (CRA) Avalon-MM Slave port On
Enable multiple MSI/MSI-X support Off
Auto Enable PCIe Interrupt (enabled at power-on) Off
Table 3–7. Avalon-MM to PCI Express Translation Settings
Parameter Value
Number of address pages 2
Size of address pages 1 MByte - 20 bits