User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
3–2 Chapter 3: Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
Running Qsys
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
As Figure 3–1 illustrates, the design example transfers data between an on-chip
memory buffer located on the Avalon-MM side and a PCI Express memory buffer
located on the root complex side. The data transfer uses the DMA component which is
programmed by the PCI Express software application running on the Root Complex
processor. The example design also includes the Transceiver Reconfiguration
Controller which allows you to dynamically reconfigure transceiver settings. This
component is necessary for high performance transceiver designs.
Running Qsys
Follow these steps to launch Qsys:
1. Choose Programs > Altera > Quartus II><version_number> (Windows Start
menu) to run the Quartus II software. Alternatively, you can also use the
Quartus II Web Edition software.
2. On the Quartus II File menu, click New.
3. Select Qsys System File and click OK. Qsys appears.
4. To establish global settings, click the Project Settings tab.
5. Specify the settings in Table 3–1.
f Refer to Creating a System with Qsys in volume 1 of the Quartus II Handbook for more
information about how to use Qsys, including information about the Project Settings
tab.
h For an explanation of each Qsys menu item, refer to About Qsys in Quartus II Help.
1 This example design requires that you specify the same name for the Qsys system as
for the top-level project file. However, this naming is not required for your own
design. If you want to choose a different name for the system file, you must create a
wrapper HDL file that matches the project top level name and instantiate the
generated system.
6. To add modules from the Component Library tab, under Interface Protocols in
the PCI folder, click the Avalon-MM Cyclone Hard IP for PCI Express
component, then click +Add.
Table 3–1. Project Settings
Parameter Value
Device family
Device
5CGXFC7D6F31C7
Clock crossing adapter type Handshake
Limit interconnect pipeline stages to 2
Generation Id 0