User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
2–16 Chapter 2: Getting Started with the Cyclone V Hard IP for PCI Express
Compiling the Design in the Qsys Design Flow
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
2. Click the browse button next the File name box and browse to the
gen1_x4_example_design/altera_pcie_<dev>_ip_ast/pcie_de_gen1_x4_ast64/
synthesis/ directory.
3. On the Quartus II File menu, click New, then New Quartus II Project, then OK.
4. Click Next in the New Project Wizard: Introduction (The introduction does not
appear if you previously turned it off.)
5. On the Directory, Name, Top-Level Entity page, enter the following information:
a. The working directory shown is correct. You do not have to change it.
b. For the project name, click the browse buttons and select your variant name,
pcie_de_gen1_x4_ast64 then click Open.r
1 If the top-level design entity and Qsys system names are identical, the
Quartus II software treats the Qsys system as the top-level design entity.
6. Click Next to display the Add Files page.
7. Complete the following steps to add the Quartus II IP File (.qip) to the project:
a. Click the browse button. The Select File dialog box appears.
b. In the Files of type list, select IP Variation Files (*.qip).
c. Click pcie_de_gen1_x4_ast64.qip and then click Open.
d. On the Add Files page, click Add, then click OK.
8. Click Next to display the Device page.
9. On the Family & Device Settings page, choose the following target device family
and options:
a. In the Family list, select Cyclone V(E/GX/GT/SX/SE/ST)
b. In the Devices list, select Cyclone V GX Extended Features
c. In the Available devices list, select5CGXFC7D6F31C7.
10. Click Next to close this page and display the EDA Tool Settings page.
11. Click Next to display the Summary page.
12. Check the Summary page to ensure that you have entered all the information
correctly.
13.
Click Finish to create the Quartus II project.