User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 2: Getting Started with the Cyclone V Hard IP for PCI Express 2–13
Qsys Design Flow
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Example 2–1. Excerpts from Transcript of Successful Simulation Run (continued)
# INFO: 8973 ns RP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 61288 ns ---------
# INFO: 61288 ns TASK:dma_rd_test
# INFO: 61288 ns ---------
# INFO: 61288 ns TASK:dma_set_rd_desc_data
#
INFO: 61288 ns ---------
# INFO: 61288 ns TASK:dma_set_msi READ
# INFO: 61288 ns Message Signaled Interrupt Configuration
# IN
FO: 61288 ns msi_address (RC memory)= 0x07F0
# INFO:
63512 ns msi_control_register = 0x0084
# I
NFO: 72440 ns msi_expected = 0xB0FC
# IN
FO: 72440 ns msi_capabilities address = 0x0050
# INFO: 72440 ns multi_message_enable = 0x0002
# INFO: 72440 ns msi_number = 0000
# INFO: 72440 ns msi_traffic_class = 0000
# INFO: 72440 ns ---------
# INFO: 72440 ns TASK:dma_set_header READ
# INFO: 72440 ns Writing Descriptor header
# INFO: 724
80 ns data content of the DT header
# INFO
: 72480 ns
# INFO: 72480 ns Shared Memory Data Display:
# INFO: 72480 ns Address Data
# INFO: 72480 ns ------- ----
# INFO: 72480 ns 00000900 00000003 00000000 00000900 CAFEFADE
#
INFO: 72480 ns ---------
# INFO: 72480 ns TASK:dma_set_rclast
# IN
FO: 72480 ns Start READ DMA : RC issues MWr (RCLast=0002)
# INFO: 72496 ns ---------
# INFO: 72509 ns TASK:msi_poll Po
lling MSI Address:07F0---> Data:FADE......
# INFO: 72693 ns TASK:rcmem_poll Polling RC Address0000090C current data
(0000FADE) expected data (00000002)
# INFO: 80693 ns TASK:rcmem_poll Polling RC Address0000090C current data
(00000000) expected data (00000002)
# INFO: 84749 ns TASK:msi_poll Received DMA Read MSI(0000) : B0FC
# I
NFO: 84893 ns TASK:rcmem_poll Polling RC Address0000090C current data
(00000002) expected data (00000002)
# INFO: 84893 ns TASK:rcmem_poll ---> Received Expected Data (00000002)
# INFO: 84901 ns ---------
# INFO: 84901 ns Completed DMA Read
# INFO: 84901 ns TASK:chained_dma_test
# INFO: 84901 ns DMA: Write
# INFO: 84901 ns ---------
# INFO: 84901 ns TASK:dma_wr_test
# INFO: 84901 ns DMA: Write
# INFO: 84901 ns ---------
# INFO: 84901 ns TASK:dm
a_set_wr_desc_data
# INFO: 84901 ns ---------
# INFO: 84901 ns TASK:dma_set_msi WRITE
# IN
FO: 84901 ns Message Signaled Interrupt Configuration
# IN
FO: 84901 ns msi_address (RC memory)= 0x07F0
# INFO:
87109 ns msi_control_register = 0x00A5
# I
NFO: 96005 ns msi_expected = 0xB0FD
# I
NFO: 96005 ns msi_capabilities address = 0x0050