User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
18–8 Chapter 18: Debugging
).Use Third-Party PCIe Analyzer
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
3. To disable the scrambler, set
test_in[2] = 1
.
4. Save altpcie_tbed_sv_hwtcl.v.
Change between the Hard and Soft Reset Controller
The Hard IP for PCI Express includes both hard and soft reset control logic. By
default, Gen1 ES and Gen1 and Gen2 production devices use the Hard Reset
Controller. Gen2 and Gen3 ES devices and Gen3 production devices use the soft reset
controller. For variants that use the hard reset controller, changing to the soft reset
controller provides greater visibility.
Complete the following steps to change to the soft reset controller:
1. Open <work_dir>/<variant>/synthesis/<variant>.v.
2. Search for the string,
hip_hard_reset_hwtcl
.
3. If
hip_hard_reset_hwtcl = 1
, the hard reset controller is active. Set
hip_hard_reset_hwtcl = 0
to change to the soft reset controller.
4. Save variant.v.
).
Use Third-Party PCIe Analyzer
A third-party logic analyzer for PCI Express records the traffic on the physical link
and decodes traffic, saving you the trouble of translating the symbols yourself. A
third-party logic analyzer can show the two-way traffic at different levels for different
requirements. For high-level diagnostics, the analyzer shows the LTSSM flows for
devices on both side of the link side-by-side. This display can help you see the link
training handshake behavior and identify where the traffic gets stuck. A traffic
analyzer can display the contents of packets so that you can verify the contents. For
complete details, refer to the third-party documentation.
BIOS Enumeration Issues
Both FPGA programming (configuration) and the initialization of a PCIe link require
time. There is some possibility that Altera FPGA including a Hard IP block for PCI
Express may not be ready when the OS/BIOS begins enumeration of the device tree.
If the FPGA is not fully programmed when the OS/BIOS begins its enumeration, the
OS does not include the Hard IP for PCI Express in its device map. To eliminate this
issue, you can do a soft reset of the system to retain the FPGA programming while
forcing the OS/BIOS to repeat its enumeration.