User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 18: Debugging 18–7
Setting Up Simulation
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
1. In the top-level testbench, which is <work_dir>/<variant>/testbench/
<variant>_tb/simulation/<variant>tb.v, change the module instantiation
parameter,
hip_ctrl_simu_mode_pipe
. to 1'b1 as shown:
pcie_de_gen1_x4_ast64 pcie_de_gen1_x4_ast64_inst
(.hip_ctrl_simu_mode_pipe ( 1'b1 )
,
2. In the top-level HDL module for the Hard IP which is work_dir>
/<variant>/testbench/<variant>_tb/simulation/submodules/<variant>.v, change
the module instantiation parameter,
enable_pipe32_sim_hwtcl
. to 1'b1 as shown:
altpcie_<dev>_hip_ast_hwtcl #( .enable_pipe32_sim_hwtcl ( 1 ),
Use the PIPE Interface for Gen1 and Gen2 Variants
Running the simulation in PIPE mode reduces simulation time and provides greater
visibility. PIPE simulation is available for Gen1 and Gen2 variants in the current
release.
Complete the following steps to simulate using the PIPE interface:
1. Change to your simulation directory,
<work_dir>/<variant>/testbench/<variant>_tb/simulation
2. Open <variant>_tb.v.
3. Search for the string,
serial_sim_hwtcl
. Set the value of this parameter to 0 if it is
1.
4. Save <variant>_tb.v.
Reduce Counter Values for Serial Simulations
You can accelerate simulation by reducing the value of counters whose default values
are set for hardware, not simulation.
Complete the following steps to reduce counter values for simulation:
1. Open <work_dir>/<variant>/testbench/<variant>_tb/simulation/submodules/
altpcie_tbed_sv_hwtcl.v.
2. Search for the string,
test_in
.
3. To reduce the value of several counters, set
test_in[0] = 1
.
4. Save altpcie_tbed_sv_hwtcl.v.
Disable the Scrambler for Gen1 and Gen2 Simulations
The 128b/130b encoding scheme implemented by the scrambler applies a binary
polynomial to the data stream to ensure enough data transitions between 0 and 1 to
prevent clock drift. The data is decoded at the other end of the link by running the
inverse polynomial.
Complete the following steps to disable the scrambler:
1. Open <work_dir>/<variant>/testbench/<variant>_tb/simulation/submodules/
altpcie_tbed_sv_hwtcl.v.
2. Search for the string,
test_in
.