User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
18–6 Chapter 18: Debugging
Recommended Reset Sequence to Avoid Link Training Issues
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
f For more information about SignalTap, refer to the Design Debugging Using the
SignalTap II Embedded Logic Analyzer chapter in volume 3 of the Quartus II Handbook.
Recommended Reset Sequence to Avoid Link Training Issues
Successful link training can only occur after the FPGA is configured and the
Transceiver Reconfiguration Controller IP Core has dynamically reconfigured
SERDES analog settings to optimize signal quality. For designs using CvP, link
training occurs after configuration of the I/O ring and Hard IP for PCI Express IP
Core. Figure 9–1 on page 9–2 shows the key signals that reset, control dynamic
reconfiguration, and link training. Successful reset sequence includes the following
steps:
1. Wait until the FPGA is configured as indicated by the assertion of
CONFIG_DONE
from the reconfig block controller.
2. Deassert the
mgmt_rst_reset
input to the Transceiver Reconfiguration Controller
IP Core.
3. Wait for
tx_cal_busy
and
rx_cal_busy
SERDES outputs to be deasserted.
4. Deassert
pin_perstn
to take the Hard IP for PCIe out of reset. For plug-in cards,
the minimum assertion time for
pin_perstn
is 100 ms. Embedded systems do not
have a minimum assertion time for
pin_perstn
.
5. Wait for the
reset_status
output to be deasserted.
6. Deassert the reset output to the Application Layer.
Setting Up Simulation
Changing the simulation parameters reduces simulation time and provides greater
visibility. Depending on the variant you are simulating, the following changes may be
useful when debugging:
■ Changing Between Serial and PIPE Simulation
■ Use the PIPE Interface for Gen1 and Gen2 Variants
■ Reduce Counter Values for Serial Simulations
■ Disable the Scrambler for Gen1 and Gen2 Simulations
Changing Between Serial and PIPE Simulation
By default, the Altera testbench runs a serial simulation. You can change between
serial and PIPE simulation by editing the top-level testbench file.
The
hip_ctrl_simu_mode_pipe
signal and the
enable_pipe32_sim_hwtcl
parameter
specify serial or PIPE simulation. When both are set to 1'b0, the simulation runs in
serial mode. When both are set to1'b1, the simulation runs in PIPE mode.
Complete the following steps to enable the 32-bit Gen3 PIPE simulation. These steps
assume that you are running the Gen1 ×4 testbench: