User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 18: Debugging 18–5
Link Hangs in L0 Due To Deassertion of tx_st_ready
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
f For more information about link training, refer to the “Link Training and Status State
Machine (LTSSM) Descriptions” section of PCI Express Base Specification 3.0.
Flow control credit
overflows
Determine if the credit field associated
with the current TLP type in the
tx_cred
bus is less than the requested
credit value. When insufficient credits
are available, the core waits for the link
partner to release the correct credit
type. Sufficient credits may be
unavailable if the link partner
increments credits more than expected,
creating a situation where the
Cyclone V Hard IP for PCI Express IP
Core credit calculation is out-of-sink
with its link partner.
Add logic to detect conditions where the
tx_st_ready
signal remains deasserted for more
than 100 cycles. Set post-triggering conditions to
check the value of the
tx_cred*
and
tx_st_*
interfaces. Add a FIFO status signal to determine if
the TXFIFO is full.
Malformed TLP is
transmitted
Refer to the log file to find the last good
packet transmitted on the link. Correlate
this packet with TLP sent on Avalon-ST
interface. Determine if the last TLP sent
has any of the following errors:
■ The actual payload sent does not
match the length field.
■ The byte enable signals violate rules
for byte enables as specified in the
Avalon Interface Specifications.
■ The format and type fields are
incorrectly specified.
■ TD field is asserted, indicating the
presence of a TLP digest (ECRC),
but the ECRC dword is not present at
the end of TLP.
■ The payload crosses a 4KByte
boundary.
Revise the Application Layer logic to correct the
error condition.
Insufficient Posted credits
released by Root Port
If a Memory Write TLP is transmitted
with a payload greater than the
maximum payload size, the Root Port
may release an incorrect posted data
credit to the End Point in simulation. As
a result, the End Point does not have
enough credits to send additional
Memory Write Requests.
Make sure Application Layer sends Memory Write
Requests with a payload less than or equal the
value specified by the maximum payload size.
Missing completion packets
or dropped packets
The RX Completion TLP might cause
the RX FIFO to overflow. Make sure that
the total outstanding read data of all
pending Memory Read Requests is
smaller than the allocated completion
credits in RX buffer.
You must ensure that the data for all outstanding
read requests does not exceed the completion
credits in the RX buffer.
Table 18–2. Link Hangs in L0 (Part 2 of 2)
Possible Causes Symptoms and Root Causes Workarounds and Solutions