User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 2: Getting Started with the Cyclone V Hard IP for PCI Express 2–11
Qsys Design Flow
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Understanding the Files Generated
Table 2–10 provides an overview of the files and directories Qsys generates.
Simulating the Example Design
Follow these steps to compile the testbench for simulation and run the chaining DMA
testbench.
1. Start your simulation tool. This example uses the ModelSim
®
software.
2. From the ModelSim transcript window, in the testbench directory
(./example_design/altera_pcie_<device>_hip_ast/<variant>/testbench/mentor)
type the following commands:
a.
do msim_setup.tcl
r
b. h r (This is the ModelSim help command.)
c. ld_debug r (This command compiles all design files and elaborates the
top-level design without any optimization.)
d. run -all r
Example 2–1 shows a partial transcript from a successful simulation. As this transcript
illustrates, the simulation includes the following stages:
■ Link training
■ Configuration
■ DMA reads and writes
Table 2–10. Qsys Generation Output Files
Directory Description
<testbench_dir>/<variant_name>/
synthesis
includes the top-level HDL file for the Hard I for PCI Express and the .qip file that
lists all of the necessary assignments and information required to process the IP
core in the Quartus II compiler. Generally, a single .qip file is generated for each IP
core.
<testbench_dir>/<variant_name>/
synthesis/submodules
Includes the HDL files necessary for Quartus II synthesis.
<testbench_dir>/<variant_name>/
testbench/
Includes testbench subdirectories for the Aldec, Cadence and Mentor simulation
tools with the required libraries and simulation scripts.
<testbench_dir>/<variant_name>/
testbench/<cad_vendor>
Includes the HDL source files and scripts for the simulation testbench.