User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 17: Testbench and Design Example 17–47
BFM Procedures and Functions
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
msi_poll Procedure
The
msi_poll
procedure tracks MSI completion from the Endpoint.
dma_set_msi Procedure
The
dma_set_msi
procedure sets PCI Express native MSI for the DMA read or the
DMA write.
Table 17–62. msi_poll Procedure
Location altpcietb_bfm_driver_rp.v
Syntax
msi_poll(max_number_of_msi,msi_address,msi_expected_dmawr,msi_expected_dmard,dma_wri
te,dma_read)
Arguments
max_number_of_msi
Specifies the number of MSI interrupts to wait for.
msi_address
The shared memory location to which the MSI messages will be written.
msi_expected_dmawr
When
dma_write
is set, this specifies the expected MSI data value for the
write DMA interrupts which is set by the
dma_set_msi
procedure.
msi_expected_dmard
When the
dma_read
is set, this specifies the expected MSI data value for the
read DMA interrupts which is set by the
dma_set_msi
procedure.
Dma_write
When set, poll for MSI from the DMA write module.
Dma_read
When set, poll for MSI from the DMA read module.
Table 17–63. dma_set_msi Procedure
Location altpcietb_bfm_driver_rp.v
Syntax
dma_set_msi(bar_table, bar_num, bus_num, dev_num, fun_num, direction, msi_address,
msi_data, msi_number, msi_traffic_class, multi_message_enable, msi_expected)
Arguments
bar_table
Address of the Endpoint
bar_table
structure in BFM shared memory.
bar_num
BAR number to analyze.
Bus_num
Set configuration bus number.
dev_num
Set configuration device number.
Fun_num
Set configuration function number.
Direction
When 0 the direction is read.
When 1 the direction is write.
msi_address
Specifies the location in shared memory where the MSI message data
will be stored.
msi_data
The 16-bit message data that will be stored when an MSI message is
sent. The lower bits of the message data will be modified with the
message number as per the PCI specifications.
Msi_number
Returns the MSI number to be used for these interrupts.
Msi_traffic_class
Returns the MSI traffic class value.
Multi_message_enable
Returns the MSI multi message enable status.
msi_expected
Returns the expected MSI data value, which is
msi_data
modified by the
msi_number
chosen.