User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
17–42 Chapter 17: Testbench and Design Example
BFM Procedures and Functions
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
himage16
This function creates a 16-digit hexadecimal string representation of the input
argument that can be concatenated into a larger message string and passed to
ebfm_display
.
dimage1
This function creates a one-digit decimal string representation of the input argument
that can be concatenated into a larger message string and passed to
ebfm_display
.
dimage2
This function creates a two-digit decimal string representation of the input argument
that can be concatenated into a larger message string and passed to
ebfm_display
.
Argument range
vec
Input data type reg with a range of 31:0.
Return range
string
Returns an 8-digit hexadecimal representation of the input argument, padded with leading
0s, if they are needed. Return data is type
reg
with a
range
of 64:1.
Table 17–46. himage8
Table 17–47. himage16
Location altpcietb_bfm_driver_rp.v
syntax
string:= himage(vec)
Argument range
vec
Input data type reg with a range of 63:0.
Return range
string
Returns a 16-digit hexadecimal representation of the input argument, padded with leading
0s, if they are needed. Return data is type
reg
with a
range
of 128:1.
Table 17–48. dimage1
Location altpcietb_bfm_driver_rp.v
syntax
string:= dimage(vec)
Argument range
vec
Input data type
reg
with a
range
of 31:0.
Return range
string
Returns a 1-digit decimal representation of the input argument that is padded with leading
0s if necessary. Return data is type
reg
with a
range
of 8:1.
Returns the letter U if the value cannot be represented.
Table 17–49. dimage2
Location altpcietb_bfm_driver_rp.v
syntax
string:= dimage(vec)
Argument range
vec
Input data type
reg
with a
range
of 31:0.
Return range
string
Returns a 2-digit decimal representation of the input argument that is padded with leading
0s if necessary. Return data is type
reg
with a
range
of 16:1.
Returns the letter U if the value cannot be represented.