User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information

17–40 Chapter 17: Testbench and Design Example
BFM Procedures and Functions
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
ebfm_log_set_stop_on_msg_mask Verilog HDL Function
The
ebfm_log_set_stop_on_msg_mask
procedure controls which message types stop
simulation. This procedure alters the default behavior of the simulation when errors
occur as described in the Table 17–36 on page 17–38.
ebfm_log_open Verilog HDL Function
The
ebfm_log_open
procedure opens a log file of the specified name. All displayed
messages are called by
ebfm_display
and are written to this log file as simulator
standard output.
ebfm_log_close Verilog HDL Function
The
ebfm_log_close
procedure closes the log file opened by a previous call to
ebfm_log_open
.
Verilog HDL Formatting Functions
The following procedures and functions are available in the
altpcietb_bfm_driver_rp.v. This section outlines formatting functions that are only
used by Verilog HDL. All these functions take one argument of a specified length and
return a vector of a specified length.
Table 17–40. ebfm_log_set_stop_on_msg_mask
Location altpcietb_bfm_driver_rp.v
Syntax
ebfm_log_set_stop_on_msg_mask (msg_mask)
Argument
msg_mask
This argument is
reg [EBFM_MSG_ERROR_CONTINUE:EBFM_MSG_DEBUG]
.
A 1 in a specific bit position of the
msg_mask
causes messages of the type corresponding to
the bit position to stop the simulation after the message is displayed.
Table 17–41. ebfm_log_open
Location altpcietb_bfm_driver_rp.v
Syntax
ebfm_log_open (fn)
Argument
fn
This argument is type
string
and provides the file name of log file to be opened.
Table 17–42. ebfm_log_close Procedure
Location altpcietb_bfm_driver_rp.v
Syntax
ebfm_log_close
Argument NONE