User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information

Chapter 17: Testbench and Design Example 17–39
BFM Procedures and Functions
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
ebfm_display Verilog HDL Function
The
ebfm_display
procedure or function displays a message of the specified type to
the simulation standard output and also the log file if
ebfm_log_open
is called.
A message can be suppressed, simulation can be stopped or both based on the default
settings of the message type and the value of the bit mask when each of the
procedures listed below is called. You can call one or both of these procedures based
on what messages you want displayed and whether or not you want simulation to
stop for specific messages.
■ When
ebfm_log_set_suppressed_msg_mask
is called, the display of the message
might be suppressed based on the value of the bit mask.
■ When
ebfm_log_set_stop_on_msg_mask
is called, the simulation can be stopped
after the message is displayed, based on the value of the bit mask.
ebfm_log_stop_sim Verilog HDL Function
The
ebfm_log_stop_sim
procedure stops the simulation.
ebfm_log_set_suppressed_msg_mask Verilog HDL Function
The
ebfm_log_set_suppressed_msg_mask
procedure controls which message types
are suppressed.
Table 17–37. ebfm_display Procedure
Location altpcietb_bfm_driver_rp.v
Syntax
Verilog HDL: dummy_return:=ebfm_display(msg_type, message);
Argument
msg_type
Message type for the message. Should be one of the constants defined in Table 17–36 on
page 17–38.
message
The message string is limited to a maximum of 100 characters. Also, because Verilog HDL does
not allow variable length strings, this routine strips off leading characters of 8’h00 before
displaying the message.
Return
always 0
Applies only to the Verilog HDL routine.
Table 17–38. ebfm_log_stop_sim
Location altpcietb_bfm_driver_rp.v
Syntax Verilog VHDL:
return:=ebfm_log_stop_sim(success
);
Argument
success
When set to a 1, this process stops the simulation with a message indicating successful
completion. The message is prefixed with
SUCCESS
:.
Otherwise, this process stops the simulation with a message indicating unsuccessful
completion. The message is prefixed with
FAILURE
:.
Return Always 0 This value applies only to the Verilog HDL function.
Table 17–39. ebfm_log_set_suppressed_msg_mask
Location altpcietb_bfm_driver_rp.v
Syntax
bfm_log_set_suppressed_msg_mask (msg_mask)
Argument
msg_mask
This argument is
reg [EBFM_MSG_ERROR_CONTINUE: EBFM_MSG_DEBUG].
A 1 in a specific bit position of the
msg_mask
causes messages of the type corresponding to
the bit position to be suppressed.