User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 17: Testbench and Design Example 17–35
BFM Procedures and Functions
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
ebfm_cfg_decode_bar Procedure
The
ebfm_cfg_decode_bar
procedure analyzes the information in the BAR table for
the specified BAR and returns details about the BAR attributes.
BFM Shared Memory Access Procedures
The following procedures and functions are in the Verilog HDL include file
altpcietb_bfm_driver.v. These procedures and functions support accessing the BFM
shared memory.
Shared Memory Constants
The following constants are defined in altpcietb_bfm_driver.v. They select a data
pattern in the
shmem_fill
and
shmem_chk_ok
routines. These shared memory
constants are all Verilog HDL type
integer
.
Table 17–29. ebfm_cfg_decode_bar Procedure
Location altpcietb_bfm_driver_rp.v
Syntax
ebfm_cfg_decode_bar(bar_table, bar_num, log2_size, is_mem, is_pref, is_64b)
Arguments
bar_table
Address of the Endpoint bar_table structure in BFM shared memory.
bar_num
BAR number to analyze.
log2_size
This argument is set by the procedure to the log base 2 of the size of the BAR. If the BAR is
not enabled, this argument will be set to 0.
is_mem
The procedure sets this argument to indicate if the BAR is a memory space BAR (1) or I/O
Space BAR (0).
is_pref
The procedure sets this argument to indicate if the BAR is a prefetchable BAR (1) or non-
prefetchable BAR (0).
is_64b
The procedure sets this argument to indicate if the BAR is a 64-bit BAR (1) or 32-bit BAR
(0). This is set to 1 only for the lower numbered BAR of the pair.
Table 17–30. Constants: Verilog HDL Type INTEGER
Constant Description
SHMEM_FILL_ZEROS
Specifies a data pattern of all zeros
SHMEM_FILL_BYTE_INC
Specifies a data pattern of incrementing 8-bit bytes (0x00, 0x01, 0x02, etc.)
SHMEM_FILL_WORD_INC
Specifies a data pattern of incrementing 16-bit words (0x0000, 0x0001, 0x0002, etc.)
SHMEM_FILL_DWORD_INC
Specifies a data pattern of incrementing 32-bit dwords (0x00000000, 0x00000001,
0x00000002, etc.)
SHMEM_FILL_QWORD_INC
Specifies a data pattern of incrementing 64-bit qwords (0x0000000000000000,
0x0000000000000001, 0x0000000000000002, etc.)
SHMEM_FILL_ONE
Specifies a data pattern of all ones