User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
17–30 Chapter 17: Testbench and Design Example
BFM Procedures and Functions
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
ebfm_barrd_wait Procedure
The
ebfm_barrd_wait
procedure reads a block of data from the offset of the specified
Endpoint BAR and stores it in BFM shared memory. The length can be longer than the
configured maximum read request size; the procedure breaks the request up into
multiple transactions as needed. This procedure waits until all of the completion data
is returned and places it in shared memory.
ebfm_barrd_nowt Procedure
The
ebfm_barrd_nowt
procedure reads a block of data from the offset of the specified
Endpoint BAR and stores the data in BFM shared memory. The length can be longer
than the configured maximum read request size; the procedure breaks the request up
into multiple transactions as needed. This routine returns as soon as the last read
transaction has been accepted by the VC interface module, allowing subsequent reads
to be issued immediately.
Table 17–22. ebfm_barrd_wait Procedure
Location altpcietb_bfm_driver_rp.v
Syntax
ebfm_barrd_wait(bar_table, bar_num, pcie_offset, lcladdr, byte_len, tclass)
Arguments
bar_table
Address of the Endpoint
bar_table
structure in BFM shared memory. The
bar_table structure stores the address assigned to each BAR so that the driver code
does not need to be aware of the actual assigned addresses only the Application
Layer specific offsets from the BAR.
bar_num
Number of the BAR used with
pcie_offset
to determine PCI Express address.
pcie_offset
Address offset from the BAR base.
lcladdr
BFM shared memory address where the read data is stored.
byte_len
Length, in bytes, of the data to be read. Can be 1 to the minimum of the bytes
remaining in the BAR space or BFM shared memory.
tclass
Traffic class used for the PCI Express transaction.
Table 17–23. ebfm_barrd_nowt Procedure
Location altpcietb_bfm_driver_rp.v
Syntax
ebfm_barrd_nowt(bar_table, bar_num, pcie_offset, lcladdr, byte_len, tclass)
Arguments
bar_table
Address of the Endpoint
bar_table
structure in BFM shared memory.
bar_num
Number of the BAR used with
pcie_offset
to determine PCI Express address.
pcie_offset
Address offset from the BAR base.
lcladdr
BFM shared memory address where the read data is stored.
byte_len
Length, in bytes, of the data to be read. Can be 1 to the minimum of the bytes
remaining in the BAR space or BFM shared memory.
tclass
Traffic Class to be used for the PCI Express transaction.