User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information

Chapter 17: Testbench and Design Example 17–29
BFM Procedures and Functions
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
ebfm_barwr_imm Procedure
The
ebfm_barwr_imm
procedure writes up to four bytes of data to an offset from the
specified Endpoint BAR.
byte_len
Length, in bytes, of the data written. Can be 1 to the minimum of the bytes remaining in
the BAR space or BFM shared memory.
tclass
Traffic class used for the PCI Express transaction.
Table 17–20. ebfm_barwr Procedure (Part 2 of 2)
Table 17–21. ebfm_barwr_imm Procedure
Location altpcietb_bfm_driver_rp.v
Syntax
ebfm_barwr_imm(bar_table, bar_num, pcie_offset, imm_data, byte_len, tclass)
Arguments
bar_table
Address of the Endpoint
bar_table
structure in BFM shared memory. The
bar_table
structure stores the address assigned to each BAR so that the driver code does not need
to be aware of the actual assigned addresses only the Application Layer specific offsets
from the BAR.
bar_num
Number of the BAR used with
pcie_offset
to determine PCI Express address.
pcie_offset
Address offset from the BAR base.
imm_data
Data to be written. In Verilog HDL, this argument is
reg [31:0]
.In both languages, the
bits written depend on the length as follows:
Length Bits Written
4 31 downto 0
3 23 downto 0
2 15 downto 0
1 7 downto 0
byte_len
Length of the data to be written in bytes. Maximum length is 4 bytes.
tclass
Traffic class to be used for the PCI Express transaction.