User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
17–22 Chapter 17: Testbench and Design Example
Root Port BFM
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
BFM Memory Map
The BFM shared memory is configured to be two MBytes. The BFM shared memory is
mapped into the first two MBytes of I/O space and also the first two MBytes of
memory space. When the Endpoint application generates an I/O or memory
transaction in this range, the BFM reads or writes the shared memory. For illustrations
of the shared memory and I/O address spaces, refer to Figure 17–5 on page 17–25 –
Figure 17–7 on page 17–27.
Configuration Space Bus and Device Numbering
The Root Port interface is assigned to be device number 0 on internal bus number 0.
The Endpoint can be assigned to be any device number on any bus number (greater
than 0) through the call to procedure
ebfm_cfg_rp_ep
. The specified bus number is
assigned to be the secondary bus in the Root Port Configuration Space.
Configuration of Root Port and Endpoint
Before you issue transactions to the Endpoint, you must configure the Root Port and
Endpoint Configuration Space registers. To configure these registers, call the
procedure
ebfm_cfg_rp_ep
, which is included in altpcietb_bfm_driver_rp.v.
The
ebfm_cfg_rp_ep
executes the following steps to initialize the Configuration
Space:
1. Sets the Root Port Configuration Space to enable the Root Port to send transactions
on the PCI Express link.
2. Sets the Root Port and Endpoint PCI Express Capability Device Control registers
as follows:
a. Disables
Error
Reporting
in both the Root Port and Endpoint. BFM does not
have error handling capability.
b. Enables
Relaxed
Ordering
in both Root Port and Endpoint.
c. Enables
Extended
Tags
for the Endpoint, if the Endpoint has that capability.
d. Disables
Phantom
Functions
,
Aux
Power
PM
, and
No
Snoop
in both the Root Port
and Endpoint.
e. Sets the
Max
Payload
Size
to what the Endpoint supports because the Root Port
supports the maximum payload size.
f. Sets the Root Port
Max
Read
Request
Size
to 4 KBytes because the example
Endpoint design supports breaking the read into as many completions as
necessary.
g. Sets the Endpoint
Max
Read
Request
Size
equal to the
Max Payload
Size
because the Root Port does not support breaking the read request into multiple
completions.