User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 17: Testbench and Design Example 17–11
Chaining DMA Design Examples
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Table 17–4 defines the DMA status registers. These registers are read only.
Table 17–5 describes the fields of the DMA write status register. All of these fields are
read only.
[30:28]
MSI Traffic Class
When the RC application software reads the MSI capabilities of the Endpoint, this
value is assigned by default to MSI traffic class 0. These register bits map to the
back-end signal
app_msi_tc
[2:0].
31
DT RC Last Sync
When 0, the DMA engine stops transfers when the last descriptor has been
executed. When 1, the DMA engine loops infinitely restarting with the first
descriptor when the last descriptor is completed. To stop the infinite loop, set this
bit to 0.
Table 17–3. Bit Definitions for the Control Field in the DMA Write Control Register and DMA Read Control Register
Bit Field Description
Table 17–4. Chaining DMA Status Register Definitions
Addr
(2)
Register Name
3124 2316 150
0x20
DMA Wr Status Hi
For field definitions refer to Table 17–5
0x24
DMA Wr Status Lo
Target Mem Address
Width
Write DMA Performance Counter. (Clock cycles from
time DMA header programmed until last descriptor
completes, including time to fetch descriptors.)
0x28
DMA Rd Status Hi
For field definitions refer to Table 17–6
0x2C
DMA Rd Status Lo
Max No. of Tags
Read DMA Performance Counter. The number of clocks
from the time the DMA header is programmed until the
last descriptor completes, including the time to fetch
descriptors.
0x30
Error Status
Reserved
Error Counter. Number of bad
ECRCs detected by the
Application Layer. Valid only
when ECRC forwarding is
enabled.
Note to Table 17–4:
(1) This is the Endpoint byte address offset from BAR2 or BAR3.
Table 17–5. Fields in the DMA Write Status High Register
Bit Field Description
[31:28] CDMA version Identifies the version of the chaining DMA example design.
[27:24] Reserved —
[23:21] Max payload size
The following encodings are defined:
■ 001 128 bytes
■ 001 256 bytes
■ 010 512 bytes
■ 011 1024 bytes
■ 100 2048 bytes
[20:17] Reserved —
16 Write DMA descriptor FIFO empty Indicates that there are no more descriptors pending in the write DMA.
[15:0] Write DMA EPLAST Indicates the number of the last descriptor completed by the write DMA.