User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
17–10 Chapter 17: Testbench and Design Example
Chaining DMA Design Examples
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Chaining DMA Control and Status Registers
The software application programs the chaining DMA control register located in the
Endpoint application. Table 17–2 describes the control registers which consists of four
dwords for the DMA write and four dwords for the DMA read. The DMA control
registers are read/write.
Table 17–3 describes the control fields of the of the DMA read and DMA write control
registers.
32-bit BAR4
32-bit BAR5
64-bit BAR5:4
Maps to 32 KByte target memory block. Use the rc_slave module to bypass the chaining DMA.
Expansion ROM BAR Not implemented by design example; behavior is unpredictable.
I/O Space BAR (any) Not implemented by design example; behavior is unpredictable.
Table 17–1. Design Example BAR Map
Table 17–2. Chaining DMA Control Register Definitions
(1)
Addr
(2)
Register Name 3124 2316 150
0x0
DMA Wr Cntl DW0
Control Field (refer to Table 17–3) Number of descriptors in descriptor table
0x4
DMA Wr Cntl DW1
Base Address of the Write Descriptor Table (BDT) in the RC Memory–Upper DWORD
0x8
DMA Wr Cntl DW2
Base Address of the Write Descriptor Table (BDT) in the RC Memory–Lower DWORD
0xC
DMA Wr Cntl DW3
Reserved RCLAST–Idx of last descriptor to process
0x10
DMA Rd Cntl DW0
Control Field (refer to Table 17–3) Number of descriptors in descriptor table
0x14
DMA Rd Cntl DW1
Base Address of the Read Descriptor Table (BDT) in the RC Memory–Upper DWORD
0x18
DMA Rd Cntl DW2
Base Address of the Read Descriptor Table (BDT) in the RC Memory–Lower DWORD
0x1C
DMA Rd Cntl DW3
Reserved RCLAST–Idx of the last descriptor to process
Note to Table 17–2:
(1) Refer to Figure 17–2 on page 17–5 for a block diagram of the chaining DMA design example that shows these registers.
(2) This is the Endpoint byte address offset from BAR2 or BAR3.
Table 17–3. Bit Definitions for the Control Field in the DMA Write Control Register and DMA Read Control Register
Bit Field Description
16 Reserved —
17
MSI_ENA
Enables interrupts of all descriptors. When 1, the Endpoint DMA module issues an
interrupt using MSI to the RC when each descriptor is completed. Your software
application or BFM driver can use this interrupt to monitor the DMA transfer status.
18
EPLAST_ENA
Enables the Endpoint DMA module to write the number of each descriptor back to
the EPLAST field in the descriptor table. Table 17–7 describes the descriptor table.
[24:20]
MSI Number
When your RC reads the MSI capabilities of the Endpoint, these register bits map
to the back-end MSI signals
app_msi_num
[4:0]. If there is more than one MSI, the
default mapping if all the MSIs are available, is:
■ MSI 0 = Read
■ MSI 1 = Write