User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
2–6 Chapter 2: Getting Started with the Cyclone V Hard IP for PCI Express
Customizing the Endpoint in the MegaWizard Plug-In Manager Design Flow
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
19. On the Func 0 Device tab, under PCI Express/PCI Capabilities for Func 0 turn
Function Level Reset (FLR) Off.
20. Table 2–7 lists settings for the Func0 Link tab.
21. On the Func0 MSI tab, for Number of MSI messages requested, select 4.
22. On the Func0 MSI-X tab, turn Implement MSI-X off.
23. On the Func0 Legacy Interrupt tab, select INTA.
24. Click Finish. The Generation dialog box appears.
25. Turn on Generate Example Design to generate the Endpoint, testbench, and
supporting files.
26. Click Exit.
27. Click Yes if you are prompted to add the Quartus II IP File (.qip) to the project.
The .qip is a file generated by the parameter editor contains all of the necessary
assignments and information required to process the IP core in the Quartus II
compiler. Generally, a single .qip file is generated for each IP core.
Understanding the Files Generated
Table 2–8 provides an overview of directories and files generated.
Follow these steps to generate the chaining DMA testbench from the Qsys system
design example.
1. On the Quartus II File menu, click Open.
Device ID
0x00000001
0x0000E001
Revision ID
0x00000001
0x00000001
Class Code
0x00000000
0x00FF0000
Subsystem Vendor ID
0x00000000
0x00001172
Subsystem Device ID
0x00000000
0x0000E001
Table 2–7. Link Capabilities
Parameter Value
Data link layer active reporting Off
Surprise down reporting Off
Table 2–6. Device ID Registers for Func0
Table 2–8. Qsys Generation Output Files
Directory Description
<working_dir>/<variant_name>/ Includes the files for synthesis
<working_dir>/<variant_name>_sim/
altera_pcie_<device>_hip_ast
Includes the simulation files.
<working_dir>/<variant_name>_example_design/
altera_pcie_<device>_hip_ast
Includes a Qsys testbench that connects the Endpoint to a chaining
DMA engine, Transceiver Reconfiguration Controller, and driver for the
Transceiver Reconfiguration Controller.