User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 14: Error Handling 14–3
Transaction Layer Errors
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Transaction Layer Errors
Table 14–4 describes errors detected by the Transaction Layer.
Table 14–4. Errors Detected by the Transaction Layer (Part 1 of 3)
Error Type Description
Poisoned TLP received
Uncorrectable
(non-fatal)
This error occurs if a received Transaction Layer packet has the EP
poison bit set.
The received TLP is passed to the Application Layer and the Application
Layer logic must take appropriate action in response to the poisoned
TLP. Refer to “2.7.2.2 Rules for Use of Data Poisoning” in the
PCI
Express Base Specification 2.1
for more information about poisoned
TLPs.
ECRC check failed
(1)
Uncorrectable
(non-fatal)
This error is caused by an ECRC check failing despite the fact that the
TLP is not malformed and the LCRC check is valid.
The Hard IP block handles this TLP automatically. If the TLP is a
non-posted request, the Hard IP block generates a completion with
completer abort status. In all cases the TLP is deleted in the Hard IP
block and not presented to the Application Layer.
Unsupported Request for
Endpoints
Uncorrectable
(non-fatal)
This error occurs whenever a component receives any of the following
Unsupported Requests:
■ Type 0 Configuration Requests for a non-existing function.
■ Completion transaction for which the Requester ID does not match
the bus/device.
■ Unsupported message.
■ A Type 1 Configuration Request TLP for the TLP from the PCIe link.
■ A locked memory read (MEMRDLK) on Native Endpoint.
■ A locked completion transaction.
■ A 64-bit memory transaction in which the 32 MSBs of an address are
set to 0.
■ A memory or I/O transaction for which there is no matching BAR.
■ A memory transaction when the Memory Space Enable bit (bit [1] of
the PCI Command register at Configuration Space offset 0x4) is set to
0.
■ A poisoned configuration write request (
CfgWr0
)
In all cases the TLP is deleted in the Hard IP block and not presented to
the Application Layer. If the TLP is a non-posted request, the Hard IP
block generates a completion with Unsupported Request status.
Unsupported Requests for
Root Port
Uncorrectable fatal
This error occurs whenever a component receives an Unsupported
Request including:
■ Unsupported message
■ A Type 0 Configuration Request TLP
■ A 64-bit memory transaction which the 32 MSBs of an address are
set to 0.
■ A memory transaction that does not match a Windows address